[U-Boot] [PATCH v5 1/7] ppc/p4080: Add p4080 platform immap definitions

[Scott Wood]

On Wed, Sep 23, 2009 at 01:46:04PM -0500, Kumar Gala wrote:
> +typedef struct ccsr_clk {
> +        u32     clkc0csr;       /* 0xe1000 - Core 0 Clock control/status register */
> +        u8      res1[0x1c];
> +        u32     clkc1csr;       /* 0xe1020 - Core 1 Clock control/status register */
> +        u8      res2[0x1c];
> +        u32     clkc2csr;       /* 0xe1040 - Core 2 Clock control/status register */
> +        u8      res3[0x1c];
> +        u32     clkc3csr;       /* 0xe1060 - Core 3 Clock control/status register */
> +        u8      res4[0x1c];
> +        u32     clkc4csr;       /* 0xe1080 - Core 4 Clock control/status register */
> +        u8      res5[0x1c];
> +        u32     clkc5csr;       /* 0xe10a0 - Core 5 Clock control/status register */
> +        u8      res6[0x1c];
> +        u32     clkc6csr;       /* 0xe10c0 - Core 6 Clock control/status register */
> +        u8      res7[0x1c];
> +        u32     clkc7csr;       /* 0xe10e0 - Core 7 Clock control/status register */
> +        u8      res8[0x71c];
> +        u32     pllc1gsr;       /* 0xe1800 - Cluster PLL 1 General Status Register */
> +        u8      res10[0x1c];
> +        u32     pllc2gsr;       /* 0xe1820 - Cluster PLL 2 General Status Register */
> +        u8      res11[0x1c];
> +        u32     pllc3gsr;       /* 0xe1840 - Cluster PLL 3 General Status Register */
> +        u8      res12[0x1c];
> +        u32     pllc4gsr;       /* 0xe1860 - Cluster PLL 4 General Status Register */
> +        u8      res13[0x39c];
> +        u32     pllpgsr;        /* 0xe1c00 - Platform PLL General Status Register */
> +        u8      res14[0x1c];
> +        u32     plldgsr;        /* 0xe1c20 - DDR PLL General Status Register */
> +        u8      res15[0x3dc];
> +} ccsr_clk_t;

s/spaces/tabs/

And arrays would be nice here too...

-Scott