[U-Boot] [PATCH 2/2] TI: add tnetv107x evm board support for cpsw

[Cyril Chemparathy]

This patch adds the necessary board-level hookups to get the CPSW device
working on tnetv107x evm boards.

Signed-off-by: Cyril Chemparathy <cyril at ti.com>
---
 board/ti/tnetv107xevm/sdb_board.c |  155 +++++++++++++++++++++++++++++++++++++
 include/configs/tnetv107x_evm.h   |   16 ++++
 2 files changed, 171 insertions(+), 0 deletions(-)

diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c
index 3ed1cfd..a7effd0 100644
--- a/board/ti/tnetv107xevm/sdb_board.c
+++ b/board/ti/tnetv107xevm/sdb_board.c
@@ -21,6 +21,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <netdev.h>
 #include <linux/mtd/nand.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
@@ -139,6 +140,160 @@ int dram_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+#define PHY_PAGE		22
+#define PHY_MSCR		21
+#define PHY_CSCR		16
+#define PHY_PAGE_MSCR		2
+#define PHY_PAGE_DEFAULT	0
+
+static void phy_init(char *name, int addr)
+{
+	unsigned short reg;
+
+	/* Program RXID and TXID */
+	if (miiphy_write(name, addr, PHY_PAGE, PHY_PAGE_MSCR) != 0) {
+		printf("failed to select mscr page\n");
+		return;
+	}
+
+	if (miiphy_read(name, addr, PHY_MSCR, &reg) != 0) {
+		printf("failed to read mscr\n");
+		return;
+	}
+
+	reg |= 0x3 << 4;	/* RXID and TXID */
+
+	if (miiphy_write(name, addr, PHY_MSCR, reg) != 0) {
+		printf("failed to write mscr\n");
+		return;
+	}
+
+	/* Program AutoCross */
+	if (miiphy_write(name, addr, PHY_PAGE, PHY_PAGE_DEFAULT) != 0) {
+		printf("failed to select cscr page\n");
+		return;
+	}
+
+	reg = 0x0060;
+	if (miiphy_write(name, addr, PHY_CSCR, reg) != 0) {
+		printf("failed to write cscr\n");
+		return;
+	}
+
+	/* Enable Autonegotiation */
+	if (miiphy_read(name, addr, PHY_BMCR, &reg) != 0) {
+		printf("failed to read bmcr\n");
+		return;
+	}
+
+	reg |= PHY_BMCR_AUTON;
+
+	if (miiphy_write(name, addr, PHY_BMCR, reg) != 0) {
+		printf("failed to write bmcr\n");
+		return;
+	}
+
+	/* Setup Advertisement */
+	if (miiphy_read(name, addr, PHY_ANAR, &reg) != 0) {
+		printf("failed to read anar\n");
+		return;
+	}
+
+	reg |= (0x1f << 5);
+
+	if (miiphy_write(name, addr, PHY_ANAR, reg) != 0) {
+		printf("failed to write anar\n");
+		return;
+	}
+
+	/* PHY Soft Reset */
+	if (miiphy_reset(name, addr) != 0) {
+		printf("failed to soft-reset phy\n");
+		return;
+	}
+}
+
+static void cpsw_control(int enabled)
+{
+	u32 vtp0_regs	= TNETV107X_VTP_CNTRL_0;
+	u32 vtp1_regs	= TNETV107X_VTP_CNTRL_1;
+
+
+	if (!enabled) {
+		clk_disable(TNETV107X_LPSC_ETHSS_RGMII);
+		clk_disable(TNETV107X_LPSC_ETHSS);
+		return;
+	}
+
+	clk_enable(TNETV107X_LPSC_ETHSS);
+	clk_enable(TNETV107X_LPSC_ETHSS_RGMII);
+
+	/*
+	 * This piece of hardware is horribly mangled.  For one, port
+	 * 0 and port 1 configurations are strangely mixed up in the
+	 * register space, i.e., writing to port 0 registers affects
+	 * port 1 as well.   Second, for some other equally mysterious
+	 * reason, port 1 MUST be configured before port 0.
+	 */
+	__raw_writel(0x00000000, vtp1_regs + 0x04); /* single mode  */
+	__raw_writel(0x000f0000, vtp1_regs + 0x10); /* slew slowest */
+	__raw_writel(0x00000002, vtp1_regs + 0x14); /* start	    */
+
+	__raw_writel(0x00000000, vtp0_regs + 0x04); /* single mode  */
+	__raw_writel(0x000f0000, vtp0_regs + 0x10); /* slew slowest */
+	__raw_writel(0x00000002, vtp0_regs + 0x14); /* start	    */
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x14,
+		.sliver_reg_ofs	= 0x80,
+		.phy_id		= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x34,
+		.sliver_reg_ofs	= 0xc0,
+		.phy_id		= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= TNETV107X_MDIO_BASE,
+	.cpsw_base		= TNETV107X_CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x100,
+	.slaves			= 2,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0x500,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x54,
+	.hw_stats_reg_ofs	= 0x400,
+	.mac_control		= (1 << 18)	| /* IFCTLA	*/
+				  (1 << 15)	| /* EXTEN	*/
+				  (1 << 5)	| /* MIIEN	*/
+				  (1 << 4)	| /* TXFLOWEN	*/
+				  (1 << 3),	  /* RXFLOWEN	*/
+	.control		= cpsw_control,
+	.phy_init		= phy_init,
+};
+
+int board_eth_init(bd_t *bis)
+{
+	u32 latch	= TNETV107X_ASYNC_EMIF_DATA_CE3_BASE;
+
+	clk_enable(TNETV107X_LPSC_MDIO);
+	__raw_writel(0x00000000, latch);
+	udelay(1000);
+	__raw_writel(0xffffffff, latch);
+	udelay(1000);
+
+	return cpsw_register(&cpsw_data);
+}
+#endif
+
 #ifdef CONFIG_NAND_DAVINCI
 int board_nand_init(struct nand_chip *nand)
 {
diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h
index 454e9b2..d3b509b 100644
--- a/include/configs/tnetv107x_evm.h
+++ b/include/configs/tnetv107x_evm.h
@@ -68,6 +68,17 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+
 /* Flash and environment info */
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_ENV_IS_IN_NAND
@@ -149,5 +160,10 @@
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
 
 #endif /* __CONFIG_H */
-- 
1.7.0.4