[U-Boot] [PATCH v3 7/8] nds32: add board adp-ag101 support
Macpaul Lin
macpaul at andestech.com
Fri Aug 6 10:30:51 CEST 2010
Add adp-ag101 board related settings to u-boot.
Signed-off-by: Macpaul Lin <macpaul at andestech.com>
---
MAINTAINERS | 11 +
MAKEALL | 9 +
Makefile | 10 +
board/AndesTech/adp-ag101/Makefile | 51 +++++
board/AndesTech/adp-ag101/adp-ag101.c | 77 ++++++++
board/AndesTech/adp-ag101/config.mk | 28 +++
include/configs/adp-ag101.h | 322 +++++++++++++++++++++++++++++++++
7 files changed, 508 insertions(+), 0 deletions(-)
create mode 100644 board/AndesTech/adp-ag101/Makefile
create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c
create mode 100644 board/AndesTech/adp-ag101/config.mk
create mode 100644 include/configs/adp-ag101.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4b91b0f..4783d93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1039,5 +1039,16 @@ Brent Kandetzki <brentk at teleco.com>
IP04 BF532
#########################################################################
+# NDS32 Systems: #
+# #
+# Maintainer Name, Email Address #
+# Board CPU #
+#########################################################################
+
+Macpaul Lin <macpaul at andestech.com>
+
+ ADP-AG101 N1213 (AG101 SoC)
+
+#########################################################################
# End of MAINTAINERS list #
#########################################################################
diff --git a/MAKEALL b/MAKEALL
index b34ae33..5a1f1d2 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -960,6 +960,14 @@ LIST_sh=" \
LIST_sparc="gr_xc3s_1500 gr_cpci_ax2000 gr_ep2s60 grsim grsim_leon2"
+#########################################################################
+## NDS32 Systems
+#########################################################################
+
+LIST_nds32=" \
+ adp-ag101 \
+"
+
#-----------------------------------------------------------------------
#----- for now, just run PowerPC by default -----
@@ -1018,6 +1026,7 @@ do
|coldfire \
|microblaze \
|mips|mips_el \
+ |nds32|nds32el \
|nios2 \
|ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
|sh|sh2|sh3|sh4 \
diff --git a/Makefile b/Makefile
index 4f1cb1b..6772998 100644
--- a/Makefile
+++ b/Makefile
@@ -497,6 +497,16 @@ lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
#========================================================================
+# ANDES
+#========================================================================
+
+#########################################################################
+## NDS32 adp-ag101 (n1213h hard core SoC)
+#########################################################################
+adp-ag101_config: unconfig
+ @$(MKCONFIG) $(@:_config=) nds32 n1213 $(@:_config=) AndesTech ag101
+
+#========================================================================
# PowerPC
#========================================================================
diff --git a/board/AndesTech/adp-ag101/Makefile b/board/AndesTech/adp-ag101/Makefile
new file mode 100644
index 0000000..3002b6d
--- /dev/null
+++ b/board/AndesTech/adp-ag101/Makefile
@@ -0,0 +1,51 @@
+#
+# Copyright (C) 2010 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := adp-ag101.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/AndesTech/adp-ag101/adp-ag101.c b/board/AndesTech/adp-ag101/adp-ag101.c
new file mode 100644
index 0000000..083df5b
--- /dev/null
+++ b/board/AndesTech/adp-ag101/adp-ag101.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2010 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+#include <asm/arch/ftsmc020.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG101;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x100;
+
+ ftsmc020_init(); /* initialize Flash */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->bd->bi_dram[0].start = sdram_base;
+ gd->bd->bi_dram[0].size = actual_size;
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftmac100_initialize(bd);
+}
+
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else
+ return 0;
+}
diff --git a/board/AndesTech/adp-ag101/config.mk b/board/AndesTech/adp-ag101/config.mk
new file mode 100644
index 0000000..1e0264e
--- /dev/null
+++ b/board/AndesTech/adp-ag101/config.mk
@@ -0,0 +1,28 @@
+#
+# Copyright (C) 2010 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+# Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -gdwarf-2
+TEXT_BASE = 0x03200000
+LDSCRIPT := $(SRCTREE)/arch/$(ARCH)/cpu/$(CPU)/u-boot.lds
+EXTERN_LIB += $(shell $(CC) -print-file-name=include)/../static/el/libgcc.a
diff --git a/include/configs/adp-ag101.h b/include/configs/adp-ag101.h
new file mode 100644
index 0000000..1fa4668
--- /dev/null
+++ b/include/configs/adp-ag101.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (C) 2010 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro at andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul at andestech.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*-----------------------------------------------------------------------
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101P
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*-----------------------------------------------------------------------
+ * Timer
+ */
+/* a320evb: CONFIG_SYS_HZ: 1000
+ * ag101: CONFIG_SYS_HZ: APB_CLK (ag101 original timer clock frequency)
+ *
+ * CONFIG_SYS_HZ = APB_CLK = SYS_CLK = CONFIG_SYS_CLK_FREQ /2
+ * the PWM Timer 4 uses a counter of 15625 for 10 ms, so we need
+ * it to wrap 100 times (total 1562500) to get 1 sec.
+ * #define CONFIG_HZ 1562500
+ * 1562500*25=3906250
+ *
+ * However, according to the discussion before,
+ * CONFIG_SYS_HZ at 1000 is mandatory.
+ */
+#define CONFIG_SYS_HZ 1000
+#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
+
+/*
+ * System Clock
+ * Suggested frequency lists:
+ * 16000000 -> 16.000000 MHz
+ * 18432000 -> 18.432000 MHz
+ * 22118400 -> 22.118400 MHz
+ * 83000000 -> 83.000000 MHz
+ * 33000000 -> 33.000000 MHz
+ * 36864000 -> 36.864000 MHz
+ * 48000000 -> 48.000000 MHz CONFIG_ADP_AG101
+ * 39062500 -> 39.062500 MHz CONFIG_ADP_AG101P
+ */
+#ifdef CONFIG_ADP_AG101
+#define CONFIG_SYS_CLK_FREQ 48000000
+#endif
+
+#ifdef CONFIG_ADP_AG101P
+#define CONFIG_SYS_CLK_FREQ 39062500
+#endif
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_EXT_CLK
+
+#ifndef CONFIG_EXT_CLK
+#define CONFIG_PCLK
+#endif
+
+#ifdef CONFIG_EXT_CLK
+#define TIMER_CLOCK 32768 /* EXT_CLK */
+#else
+#define TIMER_CLOCK CONFIG_SYS_HZ /* PCLK */
+#endif
+
+#define TIMER_LOAD_VAL 0xffffffff
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+ */
+#ifdef CONFIG_ADP_AG101
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (2*OSC_5MHZ)
+#define RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
+#endif
+
+#ifdef CONFIG_ADP_AG101P
+#define OSC_5MHZ (5*1000000)
+#define OSC_CLK (4*OSC_5MHZ)
+#define RTC_DIV_COUNT (0.5) /* Why?? */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1 0x99600000
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+
+#ifdef CONFIG_ADP_AG101
+#define CONFIG_SYS_NS16550_CLK (46080000 * 20) / 25 /* AG101 */
+#endif
+
+#ifdef CONFIG_ADP_AG101P
+#define CONFIG_SYS_NS16550_CLK (18432000 * 20) / 25 /* AG101P */
+#endif
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY 3
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
+
+/*-----------------------------------------------------------------------
+ * size in bytes reserved for initial data
+*/
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*-----------------------------------------------------------------------
+ * SDRAM controller configuration
+ */
+#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
+ FTSDMC020_TP0_TRP(1) | \
+ FTSDMC020_TP0_TRCD(1) | \
+ FTSDMC020_TP0_TRF(3) | \
+ FTSDMC020_TP0_TWR(1) | \
+ FTSDMC020_TP0_TCL(2))
+
+#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
+ FTSDMC020_TP1_INI_REFT(8) | \
+ FTSDMC020_TP1_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
+ FTSDMC020_BANK_DDW_X16 | \
+ FTSDMC020_BANK_DSZ_256M | \
+ FTSDMC020_BANK_MBW_32 | \
+ FTSDMC020_BANK_SIZE_64M)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x0Cf00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00000000
+#define CONFIG_SYS_MEMTEST_END 0x00200000
+
+/*-----------------------------------------------------------------------
+ * Static memory controller configuration
+ */
+
+#include <asm/arch/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS { \
+ { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
+ { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
+}
+
+#ifdef CONFIG_ADP_AG101
+/*
+ * FLASH on ADP_AG101P is connected to BANK1
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG (0x00)
+#define FTSMC020_BANK0_TIMING (0x00)
+
+
+#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+#endif
+
+#ifdef CONFIG_ADP_AG101P
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
+ FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
+ FTSMC020_BANK_SIZE_32M | \
+ FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
+ FTSMC020_TPR_CTW(3) | \
+ FTSMC020_TPR_ATI(0xf) | \
+ FTSMC020_TPR_AT2(3) | \
+ FTSMC020_TPR_WTC(3) | \
+ FTSMC020_TPR_AHT(3) | \
+ FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG (0x00)
+#define FTSMC020_BANK1_TIMING (0x00)
+
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#define PHYS_FLASH_1 0x80400000
+
+#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_FLASH_SECT_SIZE (0x10000*2*2)
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x1C0000)
+#define CONFIG_ENV_SIZE CONFIG_FLASH_SECT_SIZE
+#define CONFIG_ENV_OVERWRITE
+
+#endif /* __CONFIG_H */
--
1.7.1
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