[U-Boot] the mips cache code question ?

奥刘 happyoach at gmail.com
Wed Dec 1 07:26:00 CET 2010


Dear All:

   Recently , i have build a embedded environment with Uboot . And My Chip
is adm5120 , mips4kc code.

   In the file .\cpu\mips\cache.s , i found some code confounded .

   line 152 to line 156 :

                        cache_op Index_Store_Tag_I t0
                        PTR_ADDU t0, a2
                        bne t0, t1, 1b
                       /* fill once, so data field parity is correct */
                       PTR_LI t0, INDEX_BASE

   the code  'PTR_LI t0, INDEX_BASE'  is in the branch delay slot , so this
instruction will be implement every branch cycle.

   Is it right ?  Then the cache operation  logic seems wrong .


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