[U-Boot] the mips cache code question ?

[Andrew Dyer]

On Dec 1, 2010 12:26 AM, "奥刘" <happyoach at gmail.com> wrote:

>  In the file .\cpu\mips\cache.s , i found some code confounded .
>
>  line 152 to line 156 :
>
>                       cache_op Index_Store_Tag_I t0
>                       PTR_ADDU t0, a2
>                       bne t0, t1, 1b
>                      /* fill once, so data field parity is correct */
>                      PTR_LI t0, INDEX_BASE
>
>  the code  'PTR_LI t0, INDEX_BASE'  is in the branch delay slot , so this
> instruction will be implement every branch cycle.
>
>  Is it right ?  Then the cache operation  logic seems wrong .