[U-Boot] [PATCH v1 1/2] fsl-ddr: Fix the turnaround timing for TIMING_CFG_4

[Dave Liu]

Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.

Signed-off-by: Dave Liu <daveliu at freescale.com>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c |   17 ++++++++++++-----
 1 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 73f349f..aeb54c3 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -939,7 +939,8 @@ static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
 }
 
 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
-static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
+static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts)
 {
 	unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
 	unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
@@ -948,9 +949,15 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
 	unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 
 #if defined(CONFIG_FSL_DDR3)
-	/* We need set BL/2 + 4 for BC4 or OTF */
-	rrt = 4;	/* BL/2 + 4 clocks */
-	wwt = 4;	/* BL/2 + 4 clocks */
+	if (popts->burst_length == DDR_BL8) {
+		/* We set BL/2 for fixed BL8 */
+		rrt = 0;	/* BL/2 clocks */
+		wwt = 0;	/* BL/2 clocks */
+	} else {
+		/* We need to set BL/2 + 2 to BC4 and OTF */
+		rrt = 2;	/* BL/2 + 2 clocks */
+		wwt = 2;	/* BL/2 + 2 clocks */
+	}
 	dll_lock = 1;	/* tDLLK = 512 clocks from spec */
 #endif
 	ddr->timing_cfg_4 = (0
@@ -1348,7 +1355,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_sdram_clk_cntl(ddr, popts);
 	set_ddr_init_addr(ddr);
 	set_ddr_init_ext_addr(ddr);
-	set_timing_cfg_4(ddr);
+	set_timing_cfg_4(ddr, popts);
 	set_timing_cfg_5(ddr);
 
 	set_ddr_zq_cntl(ddr, zq_en);
-- 
1.6.4