[U-Boot] [PATCH v1 2/2] fsl-ddr: change the default burst mode for DDR3

[Dave Liu]

For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.

Signed-off-by: Dave Liu <daveliu at freescale.com>
---
should go to B2.0.3 release.

 cpu/mpc8xxx/ddr/options.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 105e758..0a6169a 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -110,8 +110,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 
 	/* Choose burst length. */
 #if defined(CONFIG_FSL_DDR3)
+#if defined(CONFIG_E500MC)
+	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
+	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
+#else
 	popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
 	popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
+#endif
 #else
 	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
 #endif
-- 
1.6.4