[U-Boot] [PATCH V4 1/3] Initial support for Marvell Orion5x SoC
Prafulla Wadaskar
prafulla at marvell.com
Mon Jan 11 12:22:47 CET 2010
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Sunday, January 10, 2010 9:34 PM
> To: U-Boot at lists.denx.de
> Subject: [U-Boot] [PATCH V4 1/3] Initial support for Marvell
> Orion5x SoC
>
> This patch adds support for the Marvell Orion5x SoC.
> It has no use alone, and must be followed by a patch
> to add Orion5x support for serial, then support for
> the ED Mini V2, an Orion5x-based product from LaCie.
>
> Signed-off-by: Albert Aribaud <albert.aribaud at free.fr>
> ---
> Patchset history
>
> V1: Initial monolithic patch.
> V2: split in three patches : orion, serial, edmini;
> checkpatch'ed, with only 6 errors, in patch 1/3,
> all 6 errors being false positives.
> V3: useless GPIO and MPP programming support removed;
> low level init added/CONFIG_SKIP_LOW_LEVEL_INIT removed.
> V4: all files licensed GPLv2-only removed;
> RAM bank size detection now uses getm_ram_size().
>
> cpu/arm926ejs/orion5x/Makefile | 51 ++++++
> cpu/arm926ejs/orion5x/cpu.c | 258
> ++++++++++++++++++++++++++++++
> cpu/arm926ejs/orion5x/dram.c | 62 +++++++
> cpu/arm926ejs/orion5x/timer.c | 181 +++++++++++++++++++++
> include/asm-arm/arch-orion5x/cpu.h | 187 +++++++++++++++++++++
> include/asm-arm/arch-orion5x/mv88f5182.h | 40 +++++
> include/asm-arm/arch-orion5x/orion5x.h | 67 ++++++++
> 7 files changed, 846 insertions(+), 0 deletions(-)
> create mode 100644 cpu/arm926ejs/orion5x/Makefile
> create mode 100644 cpu/arm926ejs/orion5x/cpu.c
> create mode 100644 cpu/arm926ejs/orion5x/dram.c
> create mode 100644 cpu/arm926ejs/orion5x/timer.c
> create mode 100644 include/asm-arm/arch-orion5x/cpu.h
> create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h
> create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
>
...snip...
> diff --git a/cpu/arm926ejs/orion5x/dram.c
> b/cpu/arm926ejs/orion5x/dram.c
> new file mode 100644
> index 0000000..af4a788
> --- /dev/null
> +++ b/cpu/arm926ejs/orion5x/dram.c
> @@ -0,0 +1,62 @@
> +/*
> + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
> + *
> + * Based on original Kirkwood support which is
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <config.h>
> +#include <asm/arch/orion5x.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define ORION5X_REG_CPUCS_WIN_BAR(x)
> (ORION5X_REGISTER(0x1500) + (x * 0x08))
> +#define ORION5X_REG_CPUCS_WIN_SZ(x)
> (ORION5X_REGISTER(0x1504) + (x * 0x08))
As pointed by wolfgang earlier, you can use c-structures here too.
-Magic numbers 1500, 1504 can be replaced by appropreate macros like- CPU_CS0_BAR, CPU_CS0_SZ
-Struct pointer can be declared in cpu.h like
#define ORION5X_SDRAM_ADRDEC_BASE (ORION5X_REGISTER(0x1500))
ref( table 114 in 5182 users manual)
I know it's coming from referenced code but lets make new code the best. Also I will be updating old code too.
> +/*
> + * orion5x_sdram_bar - reads SDRAM Base Address Register
> + */
> +u32 orion5x_sdram_bar(enum memory_bank bank)
> +{
> + u32 result = 0;
> + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
> +
> + if ((!enable) || (bank > BANK3))
> + return 0;
> +
> + result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank));
> + return result;
> +}
...snip..
> diff --git a/include/asm-arm/arch-orion5x/cpu.h
> b/include/asm-arm/arch-orion5x/cpu.h
> new file mode 100644
> index 0000000..0a33999
> --- /dev/null
> +++ b/include/asm-arm/arch-orion5x/cpu.h
> @@ -0,0 +1,187 @@
> +/*
> + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
> + *
> + * Based on original Kirorion5x_ood support which is
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ORION5X_CPU_H
> +#define _ORION5X_CPU_H
> +
> +#include <asm/system.h>
> +
> +#ifndef __ASSEMBLY__
> +
> +#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en)
> (en | (target << 4) \
> + | (attr << 8) |
> (orion5x_winctrl_calcsize(size) << 16))
> +
> +#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \
> + ((_x ? ORION5X_EGIGA0_BASE :
> ORION5X_EGIGA1_BASE) + 0x44c)
> +
> +enum memory_bank {
> + BANK0,
> + BANK1,
> + BANK2,
> + BANK3
> +};
> +
> +enum orion5x_cpu_winen {
> + ORION5X_WIN_DISABLE,
> + ORION5X_WIN_ENABLE
> +};
> +
> +enum orion5x_cpu_target {
> + ORION5X_TARGET_DRAM = 0,
> + ORION5X_TARGET_DEVICE = 1,
> + ORION5X_TARGET_PCI = 3,
> + ORION5X_TARGET_PCIE = 4,
> + ORION5X_TARGET_SASRAM = 9
> +};
> +
> +enum orion5x_cpu_attrib {
> + ORION5X_ATTR_DRAM_CS0 = 0x0e,
> + ORION5X_ATTR_DRAM_CS1 = 0x0d,
> + ORION5X_ATTR_DRAM_CS2 = 0x0b,
> + ORION5X_ATTR_DRAM_CS3 = 0x07,
> + ORION5X_ATTR_PCI_MEM = 0x59,
> + ORION5X_ATTR_PCI_IO = 0x51,
> + ORION5X_ATTR_PCIE_MEM = 0x59,
> + ORION5X_ATTR_PCIE_IO = 0x51,
> + ORION5X_ATTR_SASRAM = 0x00,
> + ORION5X_ATTR_DEV_CS0 = 0x1e,
> + ORION5X_ATTR_DEV_CS1 = 0x1d,
> + ORION5X_ATTR_DEV_CS2 = 0x1b,
> + ORION5X_ATTR_BOOTROM = 0x0f
> +};
> +
> +/*
> + * Default Device Address MAP BAR values
> + */
> +#define ORION5X_DEFADR_PCIE_MEM 0x90000000
> +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000
> +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0
> +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)
> +
> +#define ORION5X_DEFADR_PCIE_IO 0xf0000000
> +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000
> +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0
> +#define ORION5X_DEFSZ_PCIE_IO (64*1024)
> +
> +#define ORION5X_DEFADR_PCI_MEM 0x98000000
> +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
> +
> +#define ORION5X_DEFADR_PCI_IO 0xf0100000
> +#define ORION5X_DEFSZ_PCI_IO (64*1024)
> +
> +#define ORION5X_DEFADR_DEV_CS0 0xfa000000
> +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
> +
> +#define ORION5X_DEFADR_DEV_CS1 0xf8000000
> +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
> +
> +#define ORION5X_DEFADR_DEV_CS2 0xfa800000
> +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
> +
> +#define ORION5X_DEFADR_BOOTROM 0xFFF80000
> +#define ORION5X_DEFSZ_BOOTROM (512*1024)
> +
> +/*
> + * PCIE registers are used for SoC device ID and revision
> + */
> +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
> +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
> +
> +/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
> +#define MV88F5181_DEV_ID 0x5181
> +#define MV88F5181_REV_B1 3
> +#define MV88F5181L_REV_A0 8
> +#define MV88F5181L_REV_A1 9
> +/* Orion-NAS (88F5182) */
> +#define MV88F5182_DEV_ID 0x5182
> +#define MV88F5182_REV_A2 2
> +/* Orion-2 (88F5281) */
> +#define MV88F5281_DEV_ID 0x5281
> +#define MV88F5281_REV_D0 4
> +#define MV88F5281_REV_D1 5
> +#define MV88F5281_REV_D2 6
> +/* Orion-1-90 (88F6183) */
> +#define MV88F6183_DEV_ID 0x6183
> +#define MV88F6183_REV_B0 3
These are Chip specific, should be moved to mv88f5182.h and similar headers for other Supported Chips
Regards.
Prafulla . .
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