[U-Boot] [PATCH] Add support for MB86R01 from Fujitsu
Matthias Weisser
matthias.weisser at graf-syteco.de
Mon Jan 11 18:18:47 CET 2010
Signed-off-by: Matthias Weisser <matthias.weisser at graf-syteco.de>
---
common/serial.c | 3 +-
cpu/arm926ejs/jade/Makefile | 47 +++++++++
cpu/arm926ejs/jade/reset.c | 37 ++++++++
cpu/arm926ejs/jade/timer.c | 127 +++++++++++++++++++++++++
include/asm-arm/arch-jade/hardware.h | 31 ++++++
include/asm-arm/arch-jade/jade.h | 170 ++++++++++++++++++++++++++++++++++
include/serial.h | 3 +-
7 files changed, 416 insertions(+), 2 deletions(-)
create mode 100644 cpu/arm926ejs/jade/Makefile
create mode 100644 cpu/arm926ejs/jade/reset.c
create mode 100644 cpu/arm926ejs/jade/timer.c
create mode 100644 include/asm-arm/arch-jade/hardware.h
create mode 100644 include/asm-arm/arch-jade/jade.h
diff --git a/common/serial.c b/common/serial.c
index 5f9ffd7..7397608 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
|| defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \
- || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
+ || defined(CONFIG_JADE)
#if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
#if (CONFIG_CONS_INDEX==1)
return &eserial1_device;
diff --git a/cpu/arm926ejs/jade/Makefile b/cpu/arm926ejs/jade/Makefile
new file mode 100644
index 0000000..360f046
--- /dev/null
+++ b/cpu/arm926ejs/jade/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS = timer.o reset.o
+SOBJS =
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/jade/reset.c b/cpu/arm926ejs/jade/reset.c
new file mode 100644
index 0000000..820c3a1
--- /dev/null
+++ b/cpu/arm926ejs/jade/reset.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Weisser <matthias.weisser at graf-syteco.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Reset the cpu by setting software reset request bit
+ */
+void reset_cpu(ulong ignored)
+{
+ writel(0x00000002, JADE_CRG_PHYS_BASE + CRG_CRSR);
+ while (1)
+ /* NOP */;
+ /* Never reached */
+}
diff --git a/cpu/arm926ejs/jade/timer.c b/cpu/arm926ejs/jade/timer.c
new file mode 100644
index 0000000..bc20f37
--- /dev/null
+++ b/cpu/arm926ejs/jade/timer.c
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop at leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Matthias Weisser <matthias.weisser at graf-syteco.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_BASE JADE_TIMER_PHYS_BASE
+
+#define TIMER_REG_LOAD (TIMER_BASE + 0)
+#define TIMER_REG_VALUE (TIMER_BASE + 4)
+#define TIMER_REG_CONTROL (TIMER_BASE + 8)
+
+#define TIMER_FREQ (CONFIG_JADE_IOCLK / 16)
+
+static ulong timestamp;
+static ulong lastdec;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, TIMER_FREQ);
+
+ return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+ usec *= TIMER_FREQ;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+ writel(TIMER_LOAD_VAL, TIMER_REG_LOAD);
+ writel(0x86, TIMER_REG_CONTROL);
+
+ reset_timer_masked();
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+ ulong now = readl(TIMER_REG_VALUE);
+
+ if (now <= lastdec) /* normal mode (non roll) */
+ /* move stamp forward with absolut diff ticks */
+ timestamp += (lastdec - now);
+ else /* we have rollover of incrementer */
+ timestamp += lastdec + TIMER_LOAD_VAL - now;
+ lastdec = now;
+ return timestamp;
+}
+
+void reset_timer_masked(void)
+{
+ /* reset time */
+ lastdec = readl(TIMER_REG_VALUE);
+ timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = usec_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/include/asm-arm/arch-jade/hardware.h b/include/asm-arm/arch-jade/hardware.h
new file mode 100644
index 0000000..a26bdca
--- /dev/null
+++ b/include/asm-arm/arch-jade/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ * <cs at mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/jade.h>
+
+#endif
diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h
new file mode 100644
index 0000000..8640a62
--- /dev/null
+++ b/include/asm-arm/arch-jade/jade.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ *
+ * jade definitions
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ * <cs at mycable.de>
+ *
+ * (C) Copyright 2009
+ * Matthias Weisser <matthias.weisser at graf-syteco.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef JADE_H
+#define JADE_H
+
+#ifndef __ASSEMBLY__
+
+/* GPIO registers */
+struct jade_gpio{
+ uint32_t gpdr0;
+ uint32_t gpdr1;
+ uint32_t gpdr2;
+ uint32_t res;
+ uint32_t gpddr0;
+ uint32_t gpddr1;
+ uint32_t gpddr2;
+};
+
+/* PWM registers */
+struct jade_pwm{
+ uint32_t bcr;
+ uint32_t tpr;
+ uint32_t pr;
+ uint32_t dr;
+ uint32_t cr;
+ uint32_t sr;
+ uint32_t ccr;
+ uint32_t ir;
+};
+
+/* The jade chip control (CCNT) register set. */
+struct jade_ccnt{
+ uint32_t ccid;
+ uint32_t csrst;
+ uint32_t pad0[2];
+ uint32_t cist;
+ uint32_t cistm;
+ uint32_t cgpio_ist;
+ uint32_t cgpio_istm;
+ uint32_t cgpio_ip;
+ uint32_t cgpio_im;
+ uint32_t caxi_bw;
+ uint32_t caxi_ps;
+ uint32_t cmux_md;
+ uint32_t cex_pin_st;
+ uint32_t cmlb;
+ uint32_t pad1[1];
+ uint32_t cusb;
+ uint32_t pad2[41];
+ uint32_t cbsc;
+ uint32_t cdcrc;
+ uint32_t cmsr0;
+ uint32_t cmsr1;
+ uint32_t pad3[2];
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Physical Address Defines
+ */
+#define JADE_DDR2C_PHYS_BASE 0xf3000000
+#define JADE_GDC_PHYS_BASE 0xf1fc0000
+#define JADE_GDC_DISP0_PHYS_BASE 0xf1fd0000
+#define JADE_GDC_DISP1_PHYS_BASE 0xf1fd2000
+#define JADE_CCNT_PHYS_BASE 0xfff42000
+#define JADE_CAN0_PHYS_BASE 0xfff54000
+#define JADE_CAN1_PHYS_BASE 0xfff55000
+#define JADE_I2C0_PHYS_BASE 0xfff56000
+#define JADE_I2C1_PHYS_BASE 0xfff57000
+#define JADE_EHCI_PHYS_BASE 0xfff80000
+#define JADE_OHCI_PHYS_BASE 0xfff81000
+#define JADE_IRC1_PHYS_BASE 0xfffb0000
+#define JADE_MEMC_PHYS_BASE 0xfffc0000
+#define JADE_TIMER_PHYS_BASE 0xfffe0000
+#define JADE_UART0_PHYS_BASE 0xfffe1000
+#define JADE_UART1_PHYS_BASE 0xfffe2000
+#define JADE_IRCE_PHYS_BASE 0xfffe4000
+#define JADE_CRG_PHYS_BASE 0xfffe7000
+#define JADE_IRC0_PHYS_BASE 0xfffe8000
+#define JADE_GPIO_PHYS_BASE 0xfffe9000
+#define JADE_PWM0_PHYS_BASE 0xfff41000
+#define JADE_PWM1_PHYS_BASE 0xfff41100
+
+/*
+ * Offset definitions for DRAM controller
+ */
+#define DDR2C_DRIC 0x00
+#define DDR2C_DRIC1 0x02
+#define DDR2C_DRIC2 0x04
+#define DDR2C_DRCA 0x06
+#define DDR2C_DRCM 0x08
+#define DDR2C_DRCST1 0x0a
+#define DDR2C_DRCST2 0x0c
+#define DDR2C_DRCR 0x0e
+#define DDR2C_DRCF 0x20
+#define DDR2C_DRASR 0x30
+#define DDR2C_DRIMS 0x50
+#define DDR2C_DROS 0x60
+#define DDR2C_DRIBSLI 0x62
+#define DDR2C_DRIBSODT1 0x64
+#define DDR2C_DRIBSOCD 0x66
+#define DDR2C_DRIBSOCD2 0x68
+#define DDR2C_DROABA 0x70
+#define DDR2C_DROBV 0x80
+#define DDR2C_DROBS 0x84
+#define DDR2C_DROBSR1 0x86
+#define DDR2C_DROBSR2 0x88
+#define DDR2C_DROBSR3 0x8a
+#define DDR2C_DROBSR4 0x8c
+#define DDR2C_DRIMR1 0x90
+#define DDR2C_DRIMR2 0x92
+#define DDR2C_DRIMR3 0x94
+#define DDR2C_DRIMR4 0x96
+#define DDR2C_DROISR1 0x98
+#define DDR2C_DROISR2 0x9a
+
+/*
+ * Offset definitions Chip Control Module
+ */
+#define CCNT_CCID 0x00
+#define CCNT_CSRST 0x1c
+#define CCNT_CIST 0x20
+#define CCNT_CISTM 0x24
+#define CCNT_CMUX_MD 0x30
+#define CCNT_CDCRC 0xec
+
+/*
+ * Offset definitions clock reset generator
+ */
+#define CRG_CRPR 0x00
+#define CRG_CRWR 0x08
+#define CRG_CRSR 0x0c
+#define CRG_CRDA 0x10
+#define CRG_CRDB 0x14
+#define CRG_CRHA 0x18
+#define CRG_CRPA 0x1c
+#define CRG_CRPB 0x20
+#define CRG_CRHB 0x24
+#define CRG_CRAM 0x28
+
+#endif /* jade_H */
diff --git a/include/serial.h b/include/serial.h
index f2638ec..a560c71 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -25,7 +25,8 @@ extern struct serial_device * default_serial_console (void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \
- defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+ defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+ defined(CONFIG_JADE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
--
1.5.6.3
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