[U-Boot] [PATCH v2] qe: fixup the snum for MPC8569 Rev2.0

[Liu Yu]

Since 1.0 and 2.0 use different snum table,
we fixup the snum value according to SPRN_SVR.

Signed-off-by: Liu Yu <yu.liu at freescale.com>
---
v2:
change to use macro SVR_SOC_VER and IS_SVR_REV

 board/freescale/mpc8569mds/mpc8569mds.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 56854ca..9d190eb 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -524,6 +524,20 @@ static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
 	clrbits_8(&bcsr[17], BCSR17_nUSBEN);
 }
 
+static void fdt_board_fixup_qe_snum(void *blob, bd_t *bd)
+{
+	unsigned int svr;
+
+	svr = mfspr(SPRN_SVR);
+	if (SVR_SOC_VER(svr) == SVR_8569_E && IS_SVR_REV(svr, 1, 0)) {
+		do_fixup_by_compat_u32(blob, "fsl,qe",
+			"fsl,qe-num-snums", 46, 1);
+	} else {
+		do_fixup_by_compat_u32(blob, "fsl,qe",
+			"fsl,qe-num-snums", 76, 1);
+	}
+}
+
 #ifdef CONFIG_PCIE1
 static struct pci_controller pcie1_hose;
 #endif  /* CONFIG_PCIE1 */
@@ -634,5 +648,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_board_fixup_esdhc(blob, bd);
 	fdt_board_fixup_qe_uart(blob, bd);
 	fdt_board_fixup_qe_usb(blob, bd);
+	fdt_board_fixup_qe_snum(blob, bd);
 }
 #endif
-- 
1.6.4