[U-Boot] U-boot running on DDR fails to detect the CFI compliant flash

prakash bedge prakash.bedge at gmail.com
Thu Jan 21 15:23:06 CET 2010


Hi All,

At last flash detection passed. :)
I have to set one DCR register for enable flash write.

But now I am facing the debug message "flash is busy" always on save
command.
Analyzing the root cause.

Thanks all of you for your help and support.

Regards,
Prakash Bedge
On Wed, Jan 20, 2010 at 6:35 PM, Jerry Van Baren <gerald.vanbaren at ge.com>wrote:

> Hi Prakash
>
> Please quote properly and don't top post.  Your emails are very hard to
> understand.
>
>
> prakash bedge wrote:
>
>> Hi Albert and Stefan,
>>  I have used the proper commands.
>> i.e.
>> mw.b 0xfc000000 0xf0
>> mw.b 0xfc000055 0x98
>> md.b 0xfc000010
>> But still no positive results.
>> Last time I forgot to tell here, that I have commneted the for(;;) loop in
>> "hang" function after flash_init result testing in lib_ppc/board.c and then
>> I am able to run the above commands on uboot prompt.
>>  1) You're writing 32-bit words to the chip. At most it should be 16-bit
>> words, possibly even 8-bits. Try mw.w and mw.b.
>> Prakash - I tried both but no success.
>> How to crosscheck the chipwidth? Can someone tell what is chipwidth and
>> portwidth?
>> I believe I am using chipwidth - 16 and portwidth - 8. How to validate
>> this against chipwidth and portwidth?
>>
>
> Number one thing you *MUST* do is read the flash data sheets, especially
> the command interface.  Repeat until you understand.  Then try the QRY
> command sequence by hand in all the various possibilities (see thread links
> below).
>
> * In your hardware, the "55" and "AA" addresses may be shifted by one or
> two bits:
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31735>
>
> * In your hardware, the command byte lane may be one byte wide, two bytes
> wide, or four bytes wide.  This changes the 55/AA addresses and which byte
> lane(s) are used for the command.
>  * Do you have 1, 2, or 4 chips on your  board?
>  * Is your memory bus 1, 2, or 4 bytes wide?
>
> The thread links below will help explain.  Note that Robert is using the
> BDI, and thus using the BDI memory read/write commands.  You want to use
> u-boot's memory read/write commands instead.
>
> Pay special attention to these posts:
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31588>
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31723>
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31724>
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31730>
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31735>
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31787>
> <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/31501/focus=31738>
>
> Good luck,
> gvb
>
> [snip]
>


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