[U-Boot] [PATCH 1/4] powerpc/p4080: Add support for initializing SERDES
Kumar Gala
galak at kernel.crashing.org
Fri Jul 16 00:15:39 CEST 2010
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.
Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.
Signed-off-by: Li Yang <leoli at freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang at freescale.com>
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
arch/powerpc/cpu/mpc85xx/Makefile | 2 +
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 212 +++++++++++++++++++++++++
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 40 +++++
arch/powerpc/cpu/mpc85xx/p4080_serdes.c | 94 +++++++++++
arch/powerpc/include/asm/fsl_serdes.h | 11 +-
5 files changed, 357 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
create mode 100644 arch/powerpc/cpu/mpc85xx/p4080_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 6ae113a..b7c0272 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -76,6 +76,8 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
+COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
new file mode 100644
index 0000000..1c03061
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include "fsl_corenet_serdes.h"
+
+static u32 serdes_prtcl_map;
+
+#ifdef DEBUG
+static const char *serdes_prtcl_str[] = {
+ [NONE] = "NA",
+ [PCIE1] = "PCIE1",
+ [PCIE2] = "PCIE2",
+ [PCIE3] = "PCIE3",
+ [PCIE4] = "PCIE4",
+ [SATA1] = "SATA1",
+ [SATA2] = "SATA2",
+ [SRIO1] = "SRIO1",
+ [SRIO2] = "SRIO2",
+ [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
+ [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
+ [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
+ [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
+ [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
+ [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
+ [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
+ [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
+ [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+ [XAUI_FM1] = "XAUI_FM1",
+ [XAUI_FM2] = "XAUI_FM2",
+ [AURORA] = "DEBUG",
+};
+#endif
+
+static const struct {
+ int idx;
+ unsigned int lpd; /* RCW lane powerdown bit */
+ int bank;
+} lanes[SRDS_MAX_LANES] = {
+ { 0, 152, FSL_SRDS_BANK_1 },
+ { 1, 153, FSL_SRDS_BANK_1 },
+ { 2, 154, FSL_SRDS_BANK_1 },
+ { 3, 155, FSL_SRDS_BANK_1 },
+ { 4, 156, FSL_SRDS_BANK_1 },
+ { 5, 157, FSL_SRDS_BANK_1 },
+ { 6, 158, FSL_SRDS_BANK_1 },
+ { 7, 159, FSL_SRDS_BANK_1 },
+ { 8, 160, FSL_SRDS_BANK_1 },
+ { 9, 161, FSL_SRDS_BANK_1 },
+ { 16, 162, FSL_SRDS_BANK_2 },
+ { 17, 163, FSL_SRDS_BANK_2 },
+ { 18, 164, FSL_SRDS_BANK_2 },
+ { 19, 165, FSL_SRDS_BANK_2 },
+ { 20, 170, FSL_SRDS_BANK_3 },
+ { 21, 171, FSL_SRDS_BANK_3 },
+ { 22, 172, FSL_SRDS_BANK_3 },
+ { 23, 173, FSL_SRDS_BANK_3 },
+};
+
+int serdes_get_lane_idx(int lane)
+{
+ return lanes[lane].idx;
+}
+
+int serdes_get_bank(int lane)
+{
+ return lanes[lane].bank;
+}
+
+int serdes_lane_enabled(int lane)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+
+ int bank = lanes[lane].bank;
+ int word = lanes[lane].lpd / 32;
+ int bit = lanes[lane].lpd % 32;
+
+ if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD)
+ return 0;
+
+ return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit));
+}
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ /* Is serdes enabled at all? */
+ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
+ return 0;
+
+ return (1 << device) & serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int cfg;
+ serdes_corenet_t *srds_regs;
+ int lane, bank, idx;
+ enum srds_prtcl lane_prtcl;
+ long long end_tick;
+ int have_bank[SRDS_MAX_BANK] = {};
+
+ /* Is serdes enabled at all? */
+ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
+ return;
+
+ srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+ debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
+
+ if (!is_serdes_prtcl_valid(cfg)) {
+ printf("SERDES[PRTCL] = 0x%x is not valid\n", cfg);
+ return;
+ }
+
+ /* Look for banks with all lanes disabled, and power down the bank. */
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
+ if (serdes_lane_enabled(lane)) {
+ have_bank[serdes_get_bank(lane)] = 1;
+ serdes_prtcl_map |= (1 << lane_prtcl);
+ }
+ }
+
+ for (bank = 0; bank < SRDS_MAX_BANK; bank++) {
+ if (!have_bank[bank]) {
+ printf("SERDES: bank %d disabled\n", bank + 1);
+ setbits_be32(&srds_regs->bank[bank].rstctl,
+ SRDS_RSTCTL_SDPD);
+ }
+ }
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ idx = serdes_get_lane_idx(lane);
+ lane_prtcl = serdes_get_prtcl(cfg, lane);
+
+#ifdef DEBUG
+ switch (lane) {
+ case 0:
+ puts("Bank1: ");
+ break;
+ case 10:
+ puts("\nBank2: ");
+ break;
+ case 14:
+ puts("\nBank3: ");
+ break;
+ default:
+ break;
+ }
+
+ printf("%s ", serdes_prtcl_str[lane_prtcl]);
+#endif
+ }
+
+#ifdef DEBUG
+ puts("\n");
+#endif
+
+ for (idx = 0; idx < SRDS_MAX_BANK; idx++) {
+ u32 rstctl;
+
+ bank = idx;
+
+ /* Skip disabled banks */
+ if (!have_bank[bank])
+ continue;
+
+ /* reset banks for errata */
+ setbits_be32(&srds_regs->bank[bank].rstctl, SRDS_RSTCTL_RST);
+
+ /* wait for reset complete or 1-second timeout */
+ end_tick = usec2ticks(1000000) + get_ticks();
+ do {
+ rstctl = in_be32(&srds_regs->bank[bank].rstctl);
+ if (rstctl & SRDS_RSTCTL_RSTDONE)
+ break;
+ } while (end_tick > get_ticks());
+
+ if (!(rstctl & SRDS_RSTCTL_RSTDONE)) {
+ printf("SERDES: timeout resetting bank %d\n",
+ bank + 1);
+ continue;
+ }
+ }
+}
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
new file mode 100644
index 0000000..4e1f331
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Author: Roy Zang <tie-fei.zang at freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET_SERDES_H
+#define __FSL_CORENET_SERDES_H
+
+#define SRDS_MAX_LANES 18
+#define SRDS_MAX_BANK 3
+
+enum srds_bank {
+ FSL_SRDS_BANK_1 = 0,
+ FSL_SRDS_BANK_2 = 1,
+ FSL_SRDS_BANK_3 = 2,
+};
+
+int is_serdes_prtcl_valid(u32 prtcl);
+int serdes_get_lane_idx(int lane);
+int serdes_get_bank(int lane);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane);
+
+#endif /* __FSL_CORENET_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/p4080_serdes.c b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
new file mode 100644
index 0000000..eb6223c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p4080_serdes.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0x8] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0xd] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
+ SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0xe] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, SGMII_FM2_DTSEC3,
+ SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, AURORA, AURORA, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, XAUI_FM2, NONE, NONE, NONE, NONE},
+ [0x10] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ NONE, NONE, NONE, NONE},
+ [0x13] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0x16] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
+ [0x19] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4},
+ [0x1d] = {PCIE1, PCIE1, PCIE3, PCIE3, NONE, SRIO2, NONE, SRIO1,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+ [0x25] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
+ AURORA, AURORA, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1},
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl) {
+ int i;
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index c7877b9..85518eb 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -32,8 +32,15 @@ enum srds_prtcl {
SATA2,
SRIO1,
SRIO2,
- SGMII_FM1,
- SGMII_FM2,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3,
+ SGMII_FM2_DTSEC4,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
--
1.6.0.6
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