[U-Boot] [PATCH] ppc4xx: T3CORP fixes and updates
Stefan Roese
sr at denx.de
Mon Jul 19 14:24:22 CEST 2010
This patch fixes some problems for the T3CORP board. Here the list
of the changes:
- Add 600-67 and 677 CPU frequency setting to chip_config
command
- Define CONFIG_DDR_RFDC_FIXED on t3corp:
While using the "normal" auto calibration code, sometimes values for
RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang
upon relocation, while running from SDRAM). With this optimized RFDC
value we can force this register and use the auto-calibration code to
setup the remaining calibration registers.
- Increase sizes of FPGA chips selects
- EBC timing updated OEN=3 for 66 MHz EBC speed
- Change ext. IRQ2 setup to level-low active
- Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL
By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the
chip busy status. This is now used instead of the data toggle method which
is used historically by default in the common CFI driver. With this change
a problem with not written data is solved on this board, where a 32 byte
block of data is still erased instead of filled with the correct content
after these commands:
=> erase 0xfc100000 +0x1000000
.....................................................................
done
Erased 128 sectors
=> cp.b 0x100000 0xfc100000 0x1000000
Copy to Flash... done
=> cmp.b 0x100000 0xfc100000 0x1000000
byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff)
Total of 12637888 bytes were the same
Signed-off-by: Stefan Roese <sr at denx.de>
---
board/t3corp/chip_config.c | 16 +++++++++++++++-
board/t3corp/init.S | 8 +++++---
board/t3corp/t3corp.c | 2 +-
include/configs/t3corp.h | 27 +++++++++++++--------------
4 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/board/t3corp/chip_config.c b/board/t3corp/chip_config.c
index c00bf16..98ab49f 100644
--- a/board/t3corp/chip_config.c
+++ b/board/t3corp/chip_config.c
@@ -27,13 +27,27 @@
struct ppc4xx_config ppc4xx_config_val[] = {
{
- "600", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
+ "600-67", "CPU: 600 PLB: 200 OPB: 67 EBC: 67",
+ {
+ 0x86, 0x80, 0xce, 0x1f, 0x7d, 0x80, 0x00, 0xe0,
+ 0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
+ "600-100", "CPU: 600 PLB: 200 OPB: 100 EBC: 100",
{
0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0,
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
}
},
{
+ "667", "CPU: 667 PLB: 166 OPB: 83 EBC: 83",
+ {
+ 0x06, 0x80, 0xbb, 0x14, 0x99, 0x82, 0x00, 0xa0,
+ 0x40, 0x88, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+ }
+ },
+ {
"800", "CPU: 800 PLB: 200 OPB: 100 EBC: 100",
{
0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0,
diff --git a/board/t3corp/init.S b/board/t3corp/init.S
index 4a4217f..ecd35ff 100644
--- a/board/t3corp/init.S
+++ b/board/t3corp/init.S
@@ -81,11 +81,13 @@ tlbtab:
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
/* TLB-entry for FPGA(s) */
- tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_1M, CONFIG_SYS_FPGA1_BASE, 4,
+ tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_1M, CONFIG_SYS_FPGA2_BASE, 4,
+ tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
+ CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_1M, CONFIG_SYS_FPGA3_BASE, 4,
+ tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
AC_RW | SA_IG)
/* TLB-entry for OCM */
diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c
index 8ffa321..ddf5897 100644
--- a/board/t3corp/t3corp.c
+++ b/board/t3corp/t3corp.c
@@ -45,7 +45,7 @@ int board_early_init_f(void)
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
- mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
+ mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h
index 0ecc5b1..7b88601 100644
--- a/include/configs/t3corp.h
+++ b/include/configs/t3corp.h
@@ -74,8 +74,8 @@
#define CONFIG_SYS_FLASH_SIZE (64 << 20)
#define CONFIG_SYS_FPGA1_BASE 0xe0000000
-#define CONFIG_SYS_FPGA2_BASE 0xe0100000
-#define CONFIG_SYS_FPGA3_BASE 0xe0200000
+#define CONFIG_SYS_FPGA2_BASE 0xe2000000
+#define CONFIG_SYS_FPGA3_BASE 0xe4000000
#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
@@ -84,14 +84,12 @@
(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
-#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
+#define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */
#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */
-#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
-
/*
* Initial RAM & stack pointer (placed in OCM)
*/
@@ -121,6 +119,7 @@
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
@@ -144,10 +143,13 @@
/*
* DDR2 SDRAM
*/
+#define CONFIG_SYS_MBYTES_SDRAM 256
+#define CONFIG_DDR_ECC
#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
#undef CONFIG_PPC4xx_DDR_METHOD_A
+#define CONFIG_DDR_RFDC_FIXED 0x000001D7 /* optimal value */
/* DDR1/2 SDRAM Device Control Register Data Values */
/* Memory Queue */
@@ -162,9 +164,6 @@
#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
-#define CONFIG_DDR_ECC
-#define CONFIG_SYS_MBYTES_SDRAM 256
-
#define CAS_LATENCY JEDEC_MA_MR_CL_DDR2_5_0_CLK
/* DDR1/2 SDRAM Device Control Register Data Values */
@@ -417,7 +416,7 @@
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(5) | \
EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(4) | \
+ EBC_BXAP_OEN_ENCODE(3) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
@@ -426,7 +425,7 @@
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
- EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BS_32MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_32BIT)
@@ -434,7 +433,7 @@
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(5) | \
EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(4) | \
+ EBC_BXAP_OEN_ENCODE(3) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
@@ -443,7 +442,7 @@
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
- EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_32BIT)
@@ -451,7 +450,7 @@
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(5) | \
EBC_BXAP_CSN_ENCODE(0) | \
- EBC_BXAP_OEN_ENCODE(4) | \
+ EBC_BXAP_OEN_ENCODE(3) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
@@ -460,7 +459,7 @@
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
- EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BS_16MB | \
EBC_BXCR_BU_RW | \
EBC_BXCR_BW_32BIT)
--
1.7.1.1
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