[U-Boot] [PATCH] NAND: add Samsung K9LBG08UXD identifier

[Lei Wen]

Rebased version for this nand chip has one problem in detecting its
page size using in nand_base.c.
If we set page size 0 in nand_ids.c, we would get the calculation
result as page size 2048, while the true page size is 4096.

I think it is reasonable to set the 32Gigabit nand as 4k page by
default, as all nand been product in this size has
more than 4k page.

The Samsung K9LBG08UXD parts are 32Gbytes x 8 bits 3.3V parts with
the 0xD7 identifier. Add these to the list of known devices IDs.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/nand_ids.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 077c305..5dd4c54 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -110,6 +110,9 @@ struct nand_flash_dev nand_flash_ids[] = {
 	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
 	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},

+	/* 32 Gigabit */
+	{"NAND 4GiB 3,3V 8-bit",        0xD7, 4096, 4096, 0, LP_OPTIONS},
+
 	/*
 	 * Renesas AND 1 Gigabit. Those chips do not support extended id and
 	 * have a strange page/block layout !  The chosen minimum erasesize is


On Mon, Jul 19, 2010 at 8:49 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
> The Samsung K9LBG08UXD parts are 32Gbytes x 8 bits 3.3V parts with
> the 0xD7 identifier. Add this to the list of known devices IDs.
>
> Signed-off-by: Lei Wen <leiwen at marvell.com>
> ---
>  drivers/mtd/nand/nand_ids.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
> index 25b22ec..3d958d8 100644
> --- a/drivers/mtd/nand/nand_ids.c
> +++ b/drivers/mtd/nand/nand_ids.c
> @@ -111,6 +111,9 @@ struct nand_flash_dev nand_flash_ids[] = {
>        {"NAND 2GiB 1,8V 16-bit",       0xB5, 0, 2048, 0, LP_OPTIONS16},
>        {"NAND 2GiB 3,3V 16-bit",       0xC5, 0, 2048, 0, LP_OPTIONS16},
>
> +       /* 32 Gigabit */
> +       {"NAND 4GiB 3,3V 8-bit",        0xD7, 0, 4096, 0, LP_OPTIONS16},
> +
>        /*
>         * Renesas AND 1 Gigabit. Those chips do not support extended id and
>         * have a strange page/block layout !  The chosen minimum erasesize is
>