[U-Boot] Watchdog support for ppc4xx

[Mark Maestas]

Hi All,

I am not having luck with watchdog enabled on the ppc4xx target.  The
board is doing a reset before Linux gets a chance to load.  I have added
more WATCHDOG_RESET commands in the image file just to see if that helps
and it does not seem to.  Even though the reset function gets called it
is still getting reset.  According to the ppc 440 documentation the
TSR[WIS] bit should get cleared to reset the timer and the code is doing
that.  I don't understand why the board keeps resetting.  

Does anyone have experience with this?

Thanks

Mark Maestas

-----Original Message-----
From: Detlev Zundel [mailto:dzu at denx.de] 
Sent: Friday, May 21, 2010 2:06 AM
To: Wolfgang Denk
Cc: Stefan Roese; u-boot at lists.denx.de; Mark Maestas
Subject: Re: [U-Boot] Watchdog support for ppc4xx

Hi Wolfgang,

> Dear Stefan Roese,
>
> In message <201005201355.01964.sr at denx.de> you wrote:
>> 
>> > Also I would like to determine in u-boot if a
>> > reset was caused by the watchdog timer using the TSR WRS field.  If
it
>> > was reset by the watchdog we will boot into a failsafe partition to
>> > protect against system update errors.
>> > 
>> > Has anyone done something like this?
>> 
>> Such a detection is not implemented for PPC4xx. Not sure if it's
implemented 
>> for any other architecture.
>
> I think lwmon5 performs such checking; eventually this is buryied
> somewhere in the POST code.

Well, at least I know that for mpc5121 we read the reser status register
at boot and copy it to global data
(arch/powerpc/cpu/mpc512x/cpu_init.c:64).  The value is also output in
the U-Boot prompt (arch/powerpc/cpu/mpc512x/cpu.c:68) which is a nice
thing IMHO.

Checking a "git grep reset_status" one can see that something similar is
done for other PowerPC cpus as well, so I'd suggest reusing this method
for ppc4xx and providing a mechanism to access this information from a
script.

Cheers
  Detlev

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