[U-Boot] [RFC] [PATCH V1 3/4] egiga: remove references to kirkwood SoC
Albert Aribaud
albert.aribaud at free.fr
Sat Jun 26 00:01:17 CEST 2010
1. macros, types, variables, functions in egiga
refer to kirkwood even though they are not
kirkwood-specific. Rename them.
2. Kirkwood cpu.c contains part of egiga init code.
Move it back to egiga.c
3. Several egiga configuraton symbols refer to kirkwood
but are not kirkwod-specific. Rename them throughout
the whole code tree.
Signed-off-by: Albert Aribaud <albert.aribaud at free.fr>
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 18 +-
arch/arm/include/asm/arch-kirkwood/cpu.h | 3 -
arch/arm/include/asm/arch-kirkwood/kirkwood.h | 4 +-
drivers/net/Makefile | 2 +-
drivers/net/egiga.c | 341 ++++++++++---------
drivers/net/egiga.h | 466 ++++++++++++------------
include/configs/guruplug.h | 6 +-
include/configs/km_arm.h | 6 +-
include/configs/mv88f6281gtw_ge.h | 6 +-
include/configs/openrd_base.h | 6 +-
include/configs/rd6281a.h | 6 +-
include/configs/sheevaplug.h | 6 +-
include/netdev.h | 2 +-
13 files changed, 440 insertions(+), 432 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 6fc3902..e0e601f 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -315,20 +315,6 @@ int arch_cpu_init(void)
reg |= (1 << 7);
writel(reg, KW_REG_MPP_OUT_DRV_REG);
#endif
-#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
- /*
- * Set egiga port0/1 in normal functional mode
- * This is required becasue on kirkwood by default ports are in reset mode
- * OS egiga driver may not have provision to set them in normal mode
- * and if u-boot is build without network support, network may fail at OS level
- */
- reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
- reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
-#endif
#ifdef CONFIG_KIRKWOOD_PCIE_INIT
/*
* Enable PCI Express Port0
@@ -378,10 +364,10 @@ int arch_misc_init(void)
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_KIRKWOOD_EGIGA
+#ifdef CONFIG_EGIGA
int cpu_eth_init(bd_t *bis)
{
- kirkwood_egiga_initialize(bis);
+ egiga_initialize(bis);
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
index b3022a3..4868a9f 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -32,9 +32,6 @@
#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
-#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
- ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
-
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
#define SYSRST_CNT_1SEC_VAL (25*1000000)
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 2470efb..831dbbb 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -57,8 +57,8 @@
#define KW_TIMER_BASE (KW_REGISTER(0x20300))
#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
#define KW_USB20_BASE (KW_REGISTER(0x50000))
-#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
-#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
+#define EGIGA0_BASE (KW_REGISTER(0x72000))
+#define EGIGA1_BASE (KW_REGISTER(0x76000))
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8853908..a60e384 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
+COBJS-$(CONFIG_EGIGA) += egiga.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
COBJS-$(CONFIG_ETHOC) += ethoc.o
@@ -46,7 +47,6 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
index cbe4748..8d738c1 100644
--- a/drivers/net/egiga.c
+++ b/drivers/net/egiga.c
@@ -35,13 +35,16 @@
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/byteorder.h>
+#if defined (CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#endif
#include "egiga.h"
DECLARE_GLOBAL_DATA_PTR;
-#define KIRKWOOD_PHY_ADR_REQUEST 0xee
-#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
+#define EGIGA_PHY_ADR_REQUEST 0xee
+#define EGIGA_SMI_REG (((struct egiga_registers *)EGIGA0_BASE)->smi)
+#define EGIGA_PSC1_REG(base) (((struct egiga_registers *)base)->psc1)
/*
* smi_reg_read - miiphy_read callback function.
@@ -51,16 +54,16 @@ DECLARE_GLOBAL_DATA_PTR;
static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
+ if (phy_adr == EGIGA_PHY_ADR_REQUEST &&
+ reg_ofs == EGIGA_PHY_ADR_REQUEST) {
/* */
- *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
+ *data = (u16) (EGIGA_REG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
@@ -75,42 +78,42 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
return -EFAULT;
}
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = EGIGA_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = EGIGA_REG_RD(EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+ } while (smi_reg & EGIGA_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
- | KWGBE_PHY_SMI_OPCODE_READ;
+ smi_reg = (phy_adr << EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << EGIGA_SMI_REG_ADDR_OFFS)
+ | EGIGA_PHY_SMI_OPCODE_READ;
/* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+ EGIGA_REG_WR(EGIGA_SMI_REG, smi_reg);
/*wait till read value is ready */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = EGIGA_PHY_SMI_TIMEOUT;
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = EGIGA_REG_RD(EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
- } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
+ } while (!(smi_reg & EGIGA_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
- for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
+ for (timeout = 0; timeout < EGIGA_PHY_SMI_TIMEOUT; timeout++) ;
- *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
+ *data = (u16) (EGIGA_REG_RD(EGIGA_SMI_REG) & EGIGA_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
@@ -127,15 +130,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- KWGBEREG_WR(regs->phyadr, data);
+ if (phy_adr == EGIGA_PHY_ADR_REQUEST &&
+ reg_ofs == EGIGA_PHY_ADR_REQUEST) {
+ EGIGA_REG_WR(regs->phyadr, data);
return 0;
}
@@ -150,24 +153,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
}
/* wait till the SMI is not busy */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = EGIGA_PHY_SMI_TIMEOUT;
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = EGIGA_REG_RD(EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+ } while (smi_reg & EGIGA_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
- smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
+ smi_reg = (data << EGIGA_PHY_SMI_DATA_OFFS);
+ smi_reg |= (phy_adr << EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << EGIGA_SMI_REG_ADDR_OFFS);
+ smi_reg &= ~EGIGA_PHY_SMI_OPCODE_READ;
/* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+ EGIGA_REG_WR(EGIGA_SMI_REG, smi_reg);
return 0;
}
@@ -204,46 +207,46 @@ static void stop_queue(u32 * qreg)
* @regs Register struct pointer.
* @param Address decode parameter struct.
*/
-static void set_access_control(struct kwgbe_registers *regs,
- struct kwgbe_winparam *param)
+static void set_access_control(struct egiga_registers *regs,
+ struct egiga_winparam *param)
{
u32 access_prot_reg;
/* Set access control register */
- access_prot_reg = KWGBEREG_RD(regs->epap);
+ access_prot_reg = EGIGA_REG_RD(regs->epap);
/* clear window permission */
access_prot_reg &= (~(3 << (param->win * 2)));
access_prot_reg |= (param->access_ctrl << (param->win * 2));
- KWGBEREG_WR(regs->epap, access_prot_reg);
+ EGIGA_REG_WR(regs->epap, access_prot_reg);
/* Set window Size reg (SR) */
- KWGBEREG_WR(regs->barsz[param->win].size,
+ EGIGA_REG_WR(regs->barsz[param->win].size,
(((param->size / 0x10000) - 1) << 16));
/* Set window Base address reg (BA) */
- KWGBEREG_WR(regs->barsz[param->win].bar,
+ EGIGA_REG_WR(regs->barsz[param->win].bar,
(param->target | param->attrib | param->base_addr));
/* High address remap reg (HARR) */
if (param->win < 4)
- KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
+ EGIGA_REG_WR(regs->ha_remap[param->win], param->high_addr);
/* Base address enable reg (BARER) */
if (param->enable == 1)
- KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
+ EGIGA_REG_BITS_RESET(regs->bare, (1 << param->win));
else
- KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
+ EGIGA_REG_BITS_SET(regs->bare, (1 << param->win));
}
-static void set_dram_access(struct kwgbe_registers *regs)
+static void set_dram_access(struct egiga_registers *regs)
{
- struct kwgbe_winparam win_param;
+ struct egiga_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
- win_param.target = KWGBE_TARGET_DRAM;
+ win_param.target = EGIGA_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
@@ -286,19 +289,19 @@ static void set_dram_access(struct kwgbe_registers *regs)
* Go through all the DA filter tables (Unicast, Special Multicast & Other
* Multicast) and set each entry to 0.
*/
-static void port_init_mac_tables(struct kwgbe_registers *regs)
+static void port_init_mac_tables(struct egiga_registers *regs)
{
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index < 4; ++table_index)
- KWGBEREG_WR(regs->dfut[table_index], 0);
+ EGIGA_REG_WR(regs->dfut[table_index], 0);
for (table_index = 0; table_index < 64; ++table_index) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
- KWGBEREG_WR(regs->dfsmt[table_index], 0);
+ EGIGA_REG_WR(regs->dfsmt[table_index], 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
- KWGBEREG_WR(regs->dfomt[table_index], 0);
+ EGIGA_REG_WR(regs->dfomt[table_index], 0);
}
}
@@ -316,7 +319,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs)
*
* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
*/
-static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
+static int port_uc_addr(struct egiga_registers *regs, u8 uc_nibble,
int option)
{
u32 unicast_reg;
@@ -336,16 +339,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
* Clear accepts frame bit at specified unicast
* DA table entry
*/
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg = EGIGA_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ EGIGA_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
case ACCEPT_MAC_ADDR:
/* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg = EGIGA_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ EGIGA_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
default:
return 0;
@@ -356,7 +359,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
-static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
+static void port_uc_addr_set(struct egiga_registers *regs, u8 * p_addr)
{
u32 mac_h;
u32 mac_l;
@@ -365,92 +368,92 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
- KWGBEREG_WR(regs->macal, mac_l);
- KWGBEREG_WR(regs->macah, mac_h);
+ EGIGA_REG_WR(regs->macal, mac_l);
+ EGIGA_REG_WR(regs->macah, mac_h);
/* Accept frames of this address */
port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
}
/*
- * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ * egiga_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*/
-static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
+static void egiga_init_rx_desc_ring(struct egiga_device *dgbe)
{
- struct kwgbe_rxdesc *p_rx_desc;
+ struct egiga_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
- p_rx_desc = dkwgbe->p_rxdesc;
+ p_rx_desc = dgbe->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ EGIGA_BUFFER_OWNED_BY_DMA | EGIGA_RX_EN_INTERRUPT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+ p_rx_desc->buf_ptr = dgbe->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1))
- p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
+ p_rx_desc->nxtdesc_p = dgbe->p_rxdesc;
else {
- p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
- ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
+ p_rx_desc->nxtdesc_p = (struct egiga_rxdesc *)
+ ((u32) p_rx_desc + EGIGA_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
- dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
+ dgbe->p_rxdesc_curr = dgbe->p_rxdesc;
}
-static int kwgbe_init(struct eth_device *dev)
+static int egiga_init(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
- kwgbe_init_rx_desc_ring(dkwgbe);
+ egiga_init_rx_desc_ring(dgbe);
/* Clear the ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
+ EGIGA_REG_WR(regs->ic, 0);
+ EGIGA_REG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
- KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+ EGIGA_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
- KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+ EGIGA_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ port_uc_addr_set(regs, dgbe->dev.enetaddr);
/* Assign port configuration and command. */
- KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
- KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
- KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+ EGIGA_REG_WR(regs->pxc, PRT_CFG_VAL);
+ EGIGA_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+ EGIGA_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Assign port SDMA configuration */
- KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
- KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
- KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
+ EGIGA_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+ EGIGA_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
+ EGIGA_REG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
- KWGBEREG_WR(regs->pmtu, 0);
+ EGIGA_REG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
- KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
- | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
+ EGIGA_REG_WR(regs->psc0, EGIGA_MAX_RX_PACKET_9700BYTE
+ | (EGIGA_REG_RD(regs->psc0) & MRU_MASK));
/* Enable port initially */
- KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ EGIGA_REG_BITS_SET(regs->psc0, EGIGA_SERIAL_PORT_EN);
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
- KWGBEREG_WR(regs->pmtu, 0);
+ EGIGA_REG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
- KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
+ EGIGA_REG_WR(regs->rxcdp[RXUQ], (u32) dgbe->p_rxdesc_curr);
/* Enable port Rx. */
- KWGBEREG_WR(regs->rqc, (1 << RXUQ));
+ EGIGA_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
@@ -458,8 +461,8 @@ static int kwgbe_init(struct eth_device *dev)
for (i = 0; i < 5; i++) {
u16 phyadr;
- miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
+ miiphy_read(dev->name, EGIGA_PHY_ADR_REQUEST,
+ EGIGA_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
@@ -472,50 +475,50 @@ static int kwgbe_init(struct eth_device *dev)
return 0;
}
-static int kwgbe_halt(struct eth_device *dev)
+static int egiga_halt(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
/* Disable all gigE address decoder */
- KWGBEREG_WR(regs->bare, 0x3f);
+ EGIGA_REG_WR(regs->bare, 0x3f);
stop_queue(®s->tqc);
stop_queue(®s->rqc);
/* Disable port */
- KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ EGIGA_REG_BITS_RESET(regs->psc0, EGIGA_SERIAL_PORT_EN);
/* Set port is not reset */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
+ EGIGA_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
/* Set MMI interface up */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
+ EGIGA_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
/* Disable & mask ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- KWGBEREG_WR(regs->pim, 0);
- KWGBEREG_WR(regs->peim, 0);
+ EGIGA_REG_WR(regs->ic, 0);
+ EGIGA_REG_WR(regs->ice, 0);
+ EGIGA_REG_WR(regs->pim, 0);
+ EGIGA_REG_WR(regs->peim, 0);
return 0;
}
-static int kwgbe_write_hwaddr(struct eth_device *dev)
+static int egiga_write_hwaddr(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
/* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ port_uc_addr_set(regs, dgbe->dev.enetaddr);
return 0;
}
-static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
+static int egiga_send(struct eth_device *dev, volatile void *dataptr,
int datasize)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
+ struct egiga_txdesc *p_txdesc = dgbe->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
@@ -527,30 +530,30 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return -1;
}
- memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
- p = dkwgbe->p_aligned_txbuf;
+ memcpy(dgbe->p_aligned_txbuf, p, datasize);
+ p = dgbe->p_aligned_txbuf;
}
- p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
- p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
- p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
+ p_txdesc->cmd_sts = EGIGA_ZERO_PADDING | EGIGA_GEN_CRC;
+ p_txdesc->cmd_sts |= EGIGA_TX_FIRST_DESC | EGIGA_TX_LAST_DESC;
+ p_txdesc->cmd_sts |= EGIGA_BUFFER_OWNED_BY_DMA;
+ p_txdesc->cmd_sts |= EGIGA_TX_EN_INTERRUPT;
p_txdesc->buf_ptr = (u8 *) p;
p_txdesc->byte_cnt = datasize;
/* Apply send command using zeroth TXUQ */
- KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
- KWGBEREG_WR(regs->tqc, (1 << TXUQ));
+ EGIGA_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+ EGIGA_REG_WR(regs->tqc, (1 << TXUQ));
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+ while (cmd_sts & EGIGA_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
- if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
- (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
- cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
+ if ((cmd_sts & (EGIGA_ERROR_SUMMARY | EGIGA_TX_LAST_FRAME)) ==
+ (EGIGA_ERROR_SUMMARY | EGIGA_TX_LAST_FRAME) &&
+ cmd_sts & (EGIGA_UR_ERROR | EGIGA_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
@@ -559,22 +562,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return 0;
}
-static int kwgbe_recv(struct eth_device *dev)
+static int egiga_recv(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_rxdesc *p_rxdesc_curr = dgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
/* wait untill rx packet available or timeout */
do {
- if (timeout < KWGBE_PHY_SMI_TIMEOUT)
+ if (timeout < EGIGA_PHY_SMI_TIMEOUT)
timeout++;
else {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
- } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
+ } while (readl(&p_rxdesc_curr->cmd_sts) & EGIGA_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
@@ -591,13 +594,13 @@ static int kwgbe_recv(struct eth_device *dev)
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts &
- (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
- != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
+ (EGIGA_RX_FIRST_DESC | EGIGA_RX_LAST_DESC))
+ != (EGIGA_RX_FIRST_DESC | EGIGA_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
- } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
+ } else if (cmd_sts & EGIGA_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
@@ -615,62 +618,82 @@ static int kwgbe_recv(struct eth_device *dev)
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ EGIGA_BUFFER_OWNED_BY_DMA | EGIGA_RX_EN_INTERRUPT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dgbe->p_rxdesc_curr);
return 0;
}
-int kirkwood_egiga_initialize(bd_t * bis)
+int egiga_initialize(bd_t * bis)
{
- struct kwgbe_device *dkwgbe;
+ struct egiga_device *dgbe;
struct eth_device *dev;
int devnum;
char *s;
- u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
+ u8 used_ports[MAX_GBE_DEVS] = CONFIG_EGIGA_PORTS;
+ u32 reg;
+
+#ifdef CONFIG_EGIGA_INIT
+ /*
+ * Set egiga port0/1 in normal functional mode
+ * This is required becasue on kirkwood by default ports are in reset mode
+ * OS egiga driver may not have provision to set them in normal mode
+ * and if u-boot is build without network support, network may fail at OS level
+ */
+#if defined (EGIGA0_BASE)
+ reg = readl(EGIGA_PSC1_REG(EGIGA0_BASE));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (EGIGA_PSC1_REG(EGIGA0_BASE)));
+#endif
+#if defined (EGIGA1_BASE)
+ reg = readl(EGIGA_PSC1_REG(EGIGA1_BASE));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (EGIGA_PSC1_REG(EGIGA1_BASE)));
+#endif
+#endif
- for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
+ for (devnum = 0; devnum < MAX_GBE_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
- if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
+ if (!(dgbe = malloc(sizeof(struct egiga_device))))
goto error1;
- memset(dkwgbe, 0, sizeof(struct kwgbe_device));
+ memset(dgbe, 0, sizeof(struct egiga_device));
- if (!(dkwgbe->p_rxdesc =
- (struct kwgbe_rxdesc *)memalign(PKTALIGN,
- KW_RXQ_DESC_ALIGNED_SIZE
+ if (!(dgbe->p_rxdesc =
+ (struct egiga_rxdesc *)memalign(PKTALIGN,
+ EGIGA_RXQ_DESC_ALIGNED_SIZE
* RINGSZ + 1)))
goto error2;
- if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
+ if (!(dgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
* PKTSIZE_ALIGN + 1)))
goto error3;
- if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
+ if (!(dgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
goto error4;
- if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
- memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
- free(dkwgbe->p_aligned_txbuf);
+ if (!(dgbe->p_txdesc = (struct egiga_txdesc *)
+ memalign(PKTALIGN, sizeof(struct egiga_txdesc) + 1))) {
+ free(dgbe->p_aligned_txbuf);
error4:
- free(dkwgbe->p_rxbuf);
+ free(dgbe->p_rxbuf);
error3:
- free(dkwgbe->p_rxdesc);
+ free(dgbe->p_rxdesc);
error2:
- free(dkwgbe);
+ free(dgbe);
error1:
printf("Err.. %s Failed to allocate memory\n",
__FUNCTION__);
return -1;
}
- dev = &dkwgbe->dev;
+ dev = &dgbe->dev;
/* must be less than NAMESIZE (16) */
sprintf(dev->name, "egiga%d", devnum);
@@ -678,13 +701,15 @@ int kirkwood_egiga_initialize(bd_t * bis)
/* Extract the MAC address from the environment */
switch (devnum) {
case 0:
- dkwgbe->regs = (void *)KW_EGIGA0_BASE;
+ dgbe->regs = (void *)EGIGA0_BASE;
s = "ethaddr";
break;
+#if defined (EGIGA1_BASE)
case 1:
- dkwgbe->regs = (void *)KW_EGIGA1_BASE;
+ dgbe->regs = (void *)EGIGA1_BASE;
s = "eth1addr";
break;
+#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__FUNCTION__, devnum);
@@ -702,19 +727,19 @@ int kirkwood_egiga_initialize(bd_t * bis)
eth_setenv_enetaddr(s, dev->enetaddr);
}
- dev->init = (void *)kwgbe_init;
- dev->halt = (void *)kwgbe_halt;
- dev->send = (void *)kwgbe_send;
- dev->recv = (void *)kwgbe_recv;
- dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
+ dev->init = (void *)egiga_init;
+ dev->halt = (void *)egiga_halt;
+ dev->send = (void *)egiga_send;
+ dev->recv = (void *)egiga_recv;
+ dev->write_hwaddr = (void *)egiga_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
- miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+ miiphy_write(dev->name, EGIGA_PHY_ADR_REQUEST,
+ EGIGA_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;
diff --git a/drivers/net/egiga.h b/drivers/net/egiga.h
index 30c773c..f758d3c 100644
--- a/drivers/net/egiga.h
+++ b/drivers/net/egiga.h
@@ -28,7 +28,7 @@
#ifndef __EGIGA_H__
#define __EGIGA_H__
-#define MAX_KWGBE_DEVS 2 /*controller has two ports */
+#define MAX_GBE_DEVS 2 /*controller has two ports */
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
@@ -49,60 +49,60 @@
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
-#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
-#define KWGBEREG_WR(adr, val) writel(val, &adr)
-#define KWGBEREG_RD(adr) readl(&adr)
-#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
-#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
+#define to_dgbe(_ed) container_of(_ed, struct egiga_device, dev)
+#define EGIGA_REG_WR(adr, val) writel(val, &adr)
+#define EGIGA_REG_RD(adr) readl(&adr)
+#define EGIGA_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
+#define EGIGA_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
- KWGBE_UCAST_MOD_NRML | \
- KWGBE_DFLT_RXQ(RXUQ) | \
- KWGBE_DFLT_RX_ARPQ(RXUQ) | \
- KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
- KWGBE_RX_BC_IF_IP | \
- KWGBE_RX_BC_IF_ARP | \
- KWGBE_CPTR_TCP_FRMS_DIS | \
- KWGBE_CPTR_UDP_FRMS_DIS | \
- KWGBE_DFLT_RX_TCPQ(RXUQ) | \
- KWGBE_DFLT_RX_UDPQ(RXUQ) | \
- KWGBE_DFLT_RX_BPDUQ(RXUQ))
+ EGIGA_UCAST_MOD_NRML | \
+ EGIGA_DFLT_RXQ(RXUQ) | \
+ EGIGA_DFLT_RX_ARPQ(RXUQ) | \
+ EGIGA_RX_BC_IF_NOT_IP_OR_ARP | \
+ EGIGA_RX_BC_IF_IP | \
+ EGIGA_RX_BC_IF_ARP | \
+ EGIGA_CPTR_TCP_FRMS_DIS | \
+ EGIGA_CPTR_UDP_FRMS_DIS | \
+ EGIGA_DFLT_RX_TCPQ(RXUQ) | \
+ EGIGA_DFLT_RX_UDPQ(RXUQ) | \
+ EGIGA_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
- KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
- KWGBE_PARTITION_DIS | \
- KWGBE_TX_CRC_GENERATION_EN
+ EGIGA_SPAN_BPDU_PACKETS_AS_NORMAL | \
+ EGIGA_PARTITION_DIS | \
+ EGIGA_TX_CRC_GENERATION_EN
-#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
+#define GT_EGIGA_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
- KWGBE_RX_BURST_SIZE_16_64BIT | \
- KWGBE_BLM_RX_NO_SWAP | \
- KWGBE_BLM_TX_NO_SWAP | \
- GT_KWGBE_IPG_INT_RX(RXUQ) | \
- KWGBE_TX_BURST_SIZE_16_64BIT)
+ EGIGA_RX_BURST_SIZE_16_64BIT | \
+ EGIGA_BLM_RX_NO_SWAP | \
+ EGIGA_BLM_TX_NO_SWAP | \
+ GT_EGIGA_IPG_INT_RX(RXUQ) | \
+ EGIGA_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE ( \
- KWGBE_FORCE_LINK_PASS | \
- KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- KWGBE_ADV_NO_FLOW_CTRL | \
- KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- KWGBE_FORCE_BP_MODE_NO_JAM | \
+ EGIGA_FORCE_LINK_PASS | \
+ EGIGA_DIS_AUTO_NEG_FOR_DUPLX | \
+ EGIGA_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ EGIGA_ADV_NO_FLOW_CTRL | \
+ EGIGA_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ EGIGA_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
- KWGBE_DO_NOT_FORCE_LINK_FAIL | \
- KWGBE_EN_AUTO_NEG_SPEED_GMII | \
- KWGBE_DTE_ADV_0 | \
- KWGBE_MIIPHY_MAC_MODE | \
- KWGBE_AUTO_NEG_NO_CHANGE | \
- KWGBE_MAX_RX_PACKET_1552BYTE | \
- KWGBE_CLR_EXT_LOOPBACK | \
- KWGBE_SET_FULL_DUPLEX_MODE | \
- KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+ EGIGA_DO_NOT_FORCE_LINK_FAIL | \
+ EGIGA_EN_AUTO_NEG_SPEED_GMII | \
+ EGIGA_DTE_ADV_0 | \
+ EGIGA_MIIPHY_MAC_MODE | \
+ EGIGA_AUTO_NEG_NO_CHANGE | \
+ EGIGA_MAX_RX_PACKET_1552BYTE | \
+ EGIGA_CLR_EXT_LOOPBACK | \
+ EGIGA_SET_FULL_DUPLEX_MODE | \
+ EGIGA_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
@@ -112,187 +112,187 @@
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define KW_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+#define EGIGA_RXQ_DESC_ALIGNED_SIZE \
+ (((sizeof(struct egiga_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
-#define KWGBE_INTERFACE_GMII_MII 0
-#define KWGBE_INTERFACE_PCM 1
-#define KWGBE_LINK_IS_DOWN 0
-#define KWGBE_LINK_IS_UP (1 << 1)
-#define KWGBE_PORT_AT_HALF_DUPLEX 0
-#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
-#define KWGBE_RX_FLOW_CTRL_DISD 0
-#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
-#define KWGBE_GMII_SPEED_100_10 0
-#define KWGBE_GMII_SPEED_1000 (1 << 4)
-#define KWGBE_MII_SPEED_10 0
-#define KWGBE_MII_SPEED_100 (1 << 5)
-#define KWGBE_NO_TX 0
-#define KWGBE_TX_IN_PROGRESS (1 << 7)
-#define KWGBE_BYPASS_NO_ACTIVE 0
-#define KWGBE_BYPASS_ACTIVE (1 << 8)
-#define KWGBE_PORT_NOT_AT_PARTN_STT 0
-#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
-#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
-#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
+#define EGIGA_INTERFACE_GMII_MII 0
+#define EGIGA_INTERFACE_PCM 1
+#define EGIGA_LINK_IS_DOWN 0
+#define EGIGA_LINK_IS_UP (1 << 1)
+#define EGIGA_PORT_AT_HALF_DUPLEX 0
+#define EGIGA_PORT_AT_FULL_DUPLEX (1 << 2)
+#define EGIGA_RX_FLOW_CTRL_DISD 0
+#define EGIGA_RX_FLOW_CTRL_ENBALED (1 << 3)
+#define EGIGA_GMII_SPEED_100_10 0
+#define EGIGA_GMII_SPEED_1000 (1 << 4)
+#define EGIGA_MII_SPEED_10 0
+#define EGIGA_MII_SPEED_100 (1 << 5)
+#define EGIGA_NO_TX 0
+#define EGIGA_TX_IN_PROGRESS (1 << 7)
+#define EGIGA_BYPASS_NO_ACTIVE 0
+#define EGIGA_BYPASS_ACTIVE (1 << 8)
+#define EGIGA_PORT_NOT_AT_PARTN_STT 0
+#define EGIGA_PORT_AT_PARTN_STT (1 << 9)
+#define EGIGA_PORT_TX_FIFO_NOT_EMPTY 0
+#define EGIGA_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
-#define KWGBE_UCAST_MOD_NRML 0
-#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
-#define KWGBE_DFLT_RXQ(_x) (_x << 1)
-#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
-#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
-#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
-#define KWGBE_RX_BC_IF_IP 0
-#define KWGBE_REJECT_BC_IF_IP (1 << 8)
-#define KWGBE_RX_BC_IF_ARP 0
-#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
-#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
-#define KWGBE_CPTR_TCP_FRMS_DIS 0
-#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
-#define KWGBE_CPTR_UDP_FRMS_DIS 0
-#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
-#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
-#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
-#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
-#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
+#define EGIGA_UCAST_MOD_NRML 0
+#define EGIGA_UNICAST_PROMISCUOUS_MODE 1
+#define EGIGA_DFLT_RXQ(_x) (_x << 1)
+#define EGIGA_DFLT_RX_ARPQ(_x) (_x << 4)
+#define EGIGA_RX_BC_IF_NOT_IP_OR_ARP 0
+#define EGIGA_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define EGIGA_RX_BC_IF_IP 0
+#define EGIGA_REJECT_BC_IF_IP (1 << 8)
+#define EGIGA_RX_BC_IF_ARP 0
+#define EGIGA_REJECT_BC_IF_ARP (1 << 9)
+#define EGIGA_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
+#define EGIGA_CPTR_TCP_FRMS_DIS 0
+#define EGIGA_CPTR_TCP_FRMS_EN (1 << 14)
+#define EGIGA_CPTR_UDP_FRMS_DIS 0
+#define EGIGA_CPTR_UDP_FRMS_EN (1 << 15)
+#define EGIGA_DFLT_RX_TCPQ(_x) (_x << 16)
+#define EGIGA_DFLT_RX_UDPQ(_x) (_x << 19)
+#define EGIGA_DFLT_RX_BPDUQ(_x) (_x << 22)
+#define EGIGA_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define KWGBE_CLASSIFY_EN 1
-#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
-#define KWGBE_PARTITION_DIS 0
-#define KWGBE_PARTITION_EN (1 << 2)
-#define KWGBE_TX_CRC_GENERATION_EN 0
-#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
+#define EGIGA_CLASSIFY_EN 1
+#define EGIGA_SPAN_BPDU_PACKETS_AS_NORMAL 0
+#define EGIGA_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
+#define EGIGA_PARTITION_DIS 0
+#define EGIGA_PARTITION_EN (1 << 2)
+#define EGIGA_TX_CRC_GENERATION_EN 0
+#define EGIGA_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define KWGBE_RIFB 1
-#define KWGBE_RX_BURST_SIZE_1_64BIT 0
-#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
-#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
-#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
-#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
-#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
-#define KWGBE_BLM_RX_BYTE_SWAP 0
-#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
-#define KWGBE_BLM_TX_BYTE_SWAP 0
-#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
-#define KWGBE_DESCRIPTORS_NO_SWAP 0
-#define KWGBE_TX_BURST_SIZE_1_64BIT 0
-#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
-#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
-#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
-#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
+#define EGIGA_RIFB 1
+#define EGIGA_RX_BURST_SIZE_1_64BIT 0
+#define EGIGA_RX_BURST_SIZE_2_64BIT (1 << 1)
+#define EGIGA_RX_BURST_SIZE_4_64BIT (1 << 2)
+#define EGIGA_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
+#define EGIGA_RX_BURST_SIZE_16_64BIT (1 << 3)
+#define EGIGA_BLM_RX_NO_SWAP (1 << 4)
+#define EGIGA_BLM_RX_BYTE_SWAP 0
+#define EGIGA_BLM_TX_NO_SWAP (1 << 5)
+#define EGIGA_BLM_TX_BYTE_SWAP 0
+#define EGIGA_DESCRIPTORS_BYTE_SWAP (1 << 6)
+#define EGIGA_DESCRIPTORS_NO_SWAP 0
+#define EGIGA_TX_BURST_SIZE_1_64BIT 0
+#define EGIGA_TX_BURST_SIZE_2_64BIT (1 << 22)
+#define EGIGA_TX_BURST_SIZE_4_64BIT (1 << 23)
+#define EGIGA_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
+#define EGIGA_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
-#define KWGBE_SERIAL_PORT_DIS 0
-#define KWGBE_SERIAL_PORT_EN 1
-#define KWGBE_FORCE_LINK_PASS (1 << 1)
-#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
-#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
-#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
-#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
-#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
-#define KWGBE_ADV_NO_FLOW_CTRL 0
-#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
-#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
-#define KWGBE_FORCE_BP_MODE_NO_JAM 0
-#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
-#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
-#define KWGBE_FORCE_LINK_FAIL 0
-#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
-#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
-#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
-#define KWGBE_DTE_ADV_0 0
-#define KWGBE_DTE_ADV_1 (1 << 14)
-#define KWGBE_MIIPHY_MAC_MODE 0
-#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
-#define KWGBE_AUTO_NEG_NO_CHANGE 0
-#define KWGBE_RESTART_AUTO_NEG (1 << 16)
-#define KWGBE_MAX_RX_PACKET_1518BYTE 0
-#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
-#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
-#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
-#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
-#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
-#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
-#define KWGBE_CLR_EXT_LOOPBACK 0
-#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
-#define KWGBE_SET_HALF_DUPLEX_MODE 0
-#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
-#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define KWGBE_SET_GMII_SPEED_TO_10_100 0
-#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
-#define KWGBE_SET_MII_SPEED_TO_10 0
-#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
+#define EGIGA_SERIAL_PORT_DIS 0
+#define EGIGA_SERIAL_PORT_EN 1
+#define EGIGA_FORCE_LINK_PASS (1 << 1)
+#define EGIGA_DO_NOT_FORCE_LINK_PASS 0
+#define EGIGA_EN_AUTO_NEG_FOR_DUPLX 0
+#define EGIGA_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
+#define EGIGA_EN_AUTO_NEG_FOR_FLOW_CTRL 0
+#define EGIGA_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
+#define EGIGA_ADV_NO_FLOW_CTRL 0
+#define EGIGA_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
+#define EGIGA_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+#define EGIGA_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
+#define EGIGA_FORCE_BP_MODE_NO_JAM 0
+#define EGIGA_FORCE_BP_MODE_JAM_TX (1 << 7)
+#define EGIGA_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
+#define EGIGA_FORCE_LINK_FAIL 0
+#define EGIGA_DO_NOT_FORCE_LINK_FAIL (1 << 10)
+#define EGIGA_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
+#define EGIGA_EN_AUTO_NEG_SPEED_GMII 0
+#define EGIGA_DTE_ADV_0 0
+#define EGIGA_DTE_ADV_1 (1 << 14)
+#define EGIGA_MIIPHY_MAC_MODE 0
+#define EGIGA_MIIPHY_PHY_MODE (1 << 15)
+#define EGIGA_AUTO_NEG_NO_CHANGE 0
+#define EGIGA_RESTART_AUTO_NEG (1 << 16)
+#define EGIGA_MAX_RX_PACKET_1518BYTE 0
+#define EGIGA_MAX_RX_PACKET_1522BYTE (1 << 17)
+#define EGIGA_MAX_RX_PACKET_1552BYTE (1 << 18)
+#define EGIGA_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
+#define EGIGA_MAX_RX_PACKET_9192BYTE (1 << 19)
+#define EGIGA_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
+#define EGIGA_SET_EXT_LOOPBACK (1 << 20)
+#define EGIGA_CLR_EXT_LOOPBACK 0
+#define EGIGA_SET_FULL_DUPLEX_MODE (1 << 21)
+#define EGIGA_SET_HALF_DUPLEX_MODE 0
+#define EGIGA_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
+#define EGIGA_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define EGIGA_SET_GMII_SPEED_TO_10_100 0
+#define EGIGA_SET_GMII_SPEED_TO_1000 (1 << 23)
+#define EGIGA_SET_MII_SPEED_TO_10 0
+#define EGIGA_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
-#define KWGBE_PHY_SMI_TIMEOUT 10000
-#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
-#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
-#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
-#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
-#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
-#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
-#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
+#define EGIGA_PHY_SMI_TIMEOUT 10000
+#define EGIGA_PHY_SMI_DATA_OFFS 0 /* Data */
+#define EGIGA_PHY_SMI_DATA_MASK (0xffff << EGIGA_PHY_SMI_DATA_OFFS)
+#define EGIGA_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
+#define EGIGA_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+#define EGIGA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
+#define EGIGA_SMI_REG_ADDR_MASK (PHYADR_MASK << EGIGA_SMI_REG_ADDR_OFFS)
+#define EGIGA_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
+#define EGIGA_PHY_SMI_OPCODE_MASK (3 << EGIGA_PHY_SMI_OPCODE_OFFS)
+#define EGIGA_PHY_SMI_OPCODE_WRITE (0 << EGIGA_PHY_SMI_OPCODE_OFFS)
+#define EGIGA_PHY_SMI_OPCODE_READ (1 << EGIGA_PHY_SMI_OPCODE_OFFS)
+#define EGIGA_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
+#define EGIGA_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
-#define KWGBE_ERROR_SUMMARY 1
+#define EGIGA_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
-#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
+#define EGIGA_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
-#define KWGBE_LC_ERROR 0
-#define KWGBE_UR_ERROR (1 << 1)
-#define KWGBE_RL_ERROR (1 << 2)
-#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
-#define KWGBE_TX_LAST_FRAME (1 << 20)
+#define EGIGA_LC_ERROR 0
+#define EGIGA_UR_ERROR (1 << 1)
+#define EGIGA_RL_ERROR (1 << 2)
+#define EGIGA_LLC_SNAP_FORMAT (1 << 9)
+#define EGIGA_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
-#define KWGBE_CRC_ERROR 0
-#define KWGBE_OVERRUN_ERROR (1 << 1)
-#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
-#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
-#define KWGBE_VLAN_TAGGED (1 << 19)
-#define KWGBE_BPDU_FRAME (1 << 20)
-#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
-#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
-#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
-#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
-#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
-#define KWGBE_FRAME_HEADER_OK (1 << 25)
-#define KWGBE_RX_LAST_DESC (1 << 26)
-#define KWGBE_RX_FIRST_DESC (1 << 27)
-#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
-#define KWGBE_RX_EN_INTERRUPT (1 << 29)
-#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
+#define EGIGA_CRC_ERROR 0
+#define EGIGA_OVERRUN_ERROR (1 << 1)
+#define EGIGA_MAX_FRAME_LENGTH_ERROR (1 << 2)
+#define EGIGA_RESOURCE_ERROR ((1 << 2) | (1 << 1))
+#define EGIGA_VLAN_TAGGED (1 << 19)
+#define EGIGA_BPDU_FRAME (1 << 20)
+#define EGIGA_TCP_FRAME_OVER_IP_V_4 0
+#define EGIGA_UDP_FRAME_OVER_IP_V_4 (1 << 21)
+#define EGIGA_OTHER_FRAME_TYPE (1 << 22)
+#define EGIGA_LAYER_2_IS_EGIGA_V_2 (1 << 23)
+#define EGIGA_FRAME_TYPE_IP_V_4 (1 << 24)
+#define EGIGA_FRAME_HEADER_OK (1 << 25)
+#define EGIGA_RX_LAST_DESC (1 << 26)
+#define EGIGA_RX_FIRST_DESC (1 << 27)
+#define EGIGA_UNKNOWN_DESTINATION_ADDR (1 << 28)
+#define EGIGA_RX_EN_INTERRUPT (1 << 29)
+#define EGIGA_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
-#define KWGBE_FRAME_FRAGMENTED (1 << 2)
+#define EGIGA_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
-#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
-#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
-#define KWGBE_TCP_FRAME 0
-#define KWGBE_UDP_FRAME (1 << 16)
-#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
-#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
-#define KWGBE_ZERO_PADDING (1 << 19)
-#define KWGBE_TX_LAST_DESC (1 << 20)
-#define KWGBE_TX_FIRST_DESC (1 << 21)
-#define KWGBE_GEN_CRC (1 << 22)
-#define KWGBE_TX_EN_INTERRUPT (1 << 23)
-#define KWGBE_AUTO_MODE (1 << 30)
+#define EGIGA_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
+#define EGIGA_FRAME_SET_TO_VLAN (1 << 15)
+#define EGIGA_TCP_FRAME 0
+#define EGIGA_UDP_FRAME (1 << 16)
+#define EGIGA_GEN_TCP_UDP_CHECKSUM (1 << 17)
+#define EGIGA_GEN_IP_V_4_CHECKSUM (1 << 18)
+#define EGIGA_ZERO_PADDING (1 << 19)
+#define EGIGA_TX_LAST_DESC (1 << 20)
+#define EGIGA_TX_FIRST_DESC (1 << 21)
+#define EGIGA_GEN_CRC (1 << 22)
+#define EGIGA_TX_EN_INTERRUPT (1 << 23)
+#define EGIGA_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
@@ -341,24 +341,24 @@
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
-struct kwgbe_barsz {
+struct egiga_barsz {
u32 bar;
u32 size;
};
-struct kwgbe_rxcdp {
- struct kwgbe_rxdesc *rxcdp;
+struct egiga_rxcdp {
+ struct egiga_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
-struct kwgbe_tqx {
+struct egiga_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
-struct kwgbe_registers {
+struct egiga_registers {
u32 phyadr;
u32 smi;
u32 euda;
@@ -372,7 +372,7 @@ struct kwgbe_registers {
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
- struct kwgbe_barsz barsz[6];
+ struct egiga_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
@@ -417,14 +417,14 @@ struct kwgbe_registers {
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
- struct kwgbe_rxcdp rxcdp[7];
- struct kwgbe_rxdesc *rxcdp7;
+ struct egiga_rxcdp rxcdp[7];
+ struct egiga_rxdesc *rxcdp7;
u32 rqc;
- struct kwgbe_txdesc *tcsdp;
+ struct egiga_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
- struct kwgbe_txdesc *tcqdp[8];
+ struct egiga_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
- struct kwgbe_tqx tqx[8];
+ struct egiga_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
@@ -447,26 +447,26 @@ struct kwgbe_registers {
};
/* structures/enums needed by driver */
-enum kwgbe_adrwin {
- KWGBE_WIN0,
- KWGBE_WIN1,
- KWGBE_WIN2,
- KWGBE_WIN3,
- KWGBE_WIN4,
- KWGBE_WIN5
+enum egiga_adrwin {
+ EGIGA_WIN0,
+ EGIGA_WIN1,
+ EGIGA_WIN2,
+ EGIGA_WIN3,
+ EGIGA_WIN4,
+ EGIGA_WIN5
};
-enum kwgbe_target {
- KWGBE_TARGET_DRAM,
- KWGBE_TARGET_DEV,
- KWGBE_TARGET_CBS,
- KWGBE_TARGET_PCI0,
- KWGBE_TARGET_PCI1
+enum egiga_target {
+ EGIGA_TARGET_DRAM,
+ EGIGA_TARGET_DEV,
+ EGIGA_TARGET_CBS,
+ EGIGA_TARGET_PCI0,
+ EGIGA_TARGET_PCI1
};
-struct kwgbe_winparam {
- enum kwgbe_adrwin win; /* Window number */
- enum kwgbe_target target; /* System targets */
+struct egiga_winparam {
+ enum egiga_adrwin win; /* Window number */
+ enum egiga_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
@@ -475,29 +475,29 @@ struct kwgbe_winparam {
u16 access_ctrl; /*Access ctrl register. see above macros */
};
-struct kwgbe_rxdesc {
+struct egiga_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
- struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+ struct egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
-struct kwgbe_txdesc {
+struct egiga_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
- struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
+ struct egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
-struct kwgbe_device {
+struct egiga_device {
struct eth_device dev;
- struct kwgbe_registers *regs;
- struct kwgbe_txdesc *p_txdesc;
- struct kwgbe_rxdesc *p_rxdesc;
- struct kwgbe_rxdesc *p_rxdesc_curr;
+ struct egiga_registers *regs;
+ struct egiga_txdesc *p_txdesc;
+ struct egiga_rxdesc *p_rxdesc;
+ struct egiga_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 2fbc6ad..367bfb1 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
@@ -172,9 +172,9 @@
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index a928c2c..6280d3d 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -47,7 +47,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
@@ -127,9 +127,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
index 96b4d1c..60453b3 100644
--- a/include/configs/mv88f6281gtw_ge.h
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
@@ -172,9 +172,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index d2f4502..3282d2d 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -47,7 +47,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
@@ -183,9 +183,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3d8e25c..3c34d7b 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
@@ -171,8 +171,8 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index e9edc44..dc9fa95 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
@@ -174,9 +174,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/netdev.h b/include/netdev.h
index 882642a..c8c38c9 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -52,6 +52,7 @@ int davinci_emac_initialize(void);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
+int egiga_initialize(bd_t *bis);
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
int ethoc_initialize(u8 dev_num, int base_addr);
int eth_3com_initialize (bd_t * bis);
@@ -61,7 +62,6 @@ int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
-int kirkwood_egiga_initialize(bd_t *bis);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
--
1.6.4.4
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