[U-Boot] [RFC] [PATCH V1 4/4] egiga: add support for orion5x
Albert Aribaud
albert.aribaud at free.fr
Sat Jun 26 00:01:18 CEST 2010
Now that egiga is detached from kirkwood, we can add
support for orion5x. This requires making the structures
representing egiga registers and descriptors volatile,
otherwise writes to them happen in the wrong order --
this did not affect kirkwood but does affect orion5x.
Signed-off-by: Albert Aribaud <albert.aribaud at free.fr>
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 14 ++
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 18 +++
arch/arm/include/asm/arch-kirkwood/cpu.h | 3 +
arch/arm/include/asm/arch-kirkwood/kirkwood.h | 3 +
arch/arm/include/asm/arch-orion5x/orion5x.h | 5 +-
board/LaCie/edminiv2/edminiv2.c | 36 +++++
board/LaCie/edminiv2/edminiv2.h | 41 +++++
drivers/net/egiga.c | 24 +---
drivers/net/egiga.h | 198 ++++++++++++------------
include/configs/edminiv2.h | 32 +++-
include/configs/guruplug.h | 2 +-
include/configs/km_arm.h | 2 +-
include/configs/mv88f6281gtw_ge.h | 2 +-
include/configs/openrd_base.h | 2 +-
include/configs/rd6281a.h | 2 +-
include/configs/sheevaplug.h | 2 +-
16 files changed, 252 insertions(+), 134 deletions(-)
create mode 100644 board/LaCie/edminiv2/edminiv2.h
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index e0e601f..8d38c85 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -315,6 +315,20 @@ int arch_cpu_init(void)
reg |= (1 << 7);
writel(reg, KW_REG_MPP_OUT_DRV_REG);
#endif
+#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
+ /*
+ * Set egiga port0/1 in normal functional mode
+ * This is required becasue on kirkwood by default ports are in reset mode
+ * OS egiga driver may not have provision to set them in normal mode
+ * and if u-boot is build without network support, network may fail at OS level
+ */
+ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
+ reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
+ reg &= ~(1 << 4); /* Clear PortReset Bit */
+ writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
+#endif
#ifdef CONFIG_KIRKWOOD_PCIE_INIT
/*
* Enable PCI Express Port0
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 03c6d06..a468c4d 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -268,3 +268,21 @@ int arch_misc_init(void)
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_EGIGA
+int cpu_eth_init(bd_t *bis)
+{
+ egiga_initialize(bis);
+ return 0;
+}
+
+/*
+ * Generates a non-random hex number just to make egiga.c happy
+ * if a MAC address has to be generated
+ */
+unsigned char get_random_hex(void)
+{
+ static unsigned char seed = 0;
+ return seed++;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h
index 4868a9f..821fa8b 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -32,6 +32,9 @@
#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
| (attr << 8) | (kw_winctrl_calcsize(size) << 16))
+#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
+ ((_x ? EGIGA0_BASE : EGIGA1_BASE) + 0x44c)
+
#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
#define SYSRST_CNT_1SEC_VAL (25*1000000)
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 831dbbb..d3a218b 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -57,8 +57,11 @@
#define KW_TIMER_BASE (KW_REGISTER(0x20300))
#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
#define KW_USB20_BASE (KW_REGISTER(0x50000))
+
+#if defined (CONFIG_EGIGA)
#define EGIGA0_BASE (KW_REGISTER(0x72000))
#define EGIGA1_BASE (KW_REGISTER(0x76000))
+#endif
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index 4008c84..d9f8a28 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -54,7 +54,10 @@
#define ORION5X_REG_PCIE_BASE (ORION5X_REGISTER(0x40000))
#define ORION5X_USB20_PORT0_BASE (ORION5X_REGISTER(0x50000))
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
-#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
+
+#if defined (CONFIG_EGIGA)
+#define EGIGA0_BASE (ORION5X_REGISTER(0x72000))
+#endif
#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 54c0ffe..d46ee4a 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <miiphy.h>
#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -90,3 +91,38 @@ int board_init(void)
return 0;
}
+
+#if defined (CONFIG_CMD_NET) && defined (CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..88e62b2
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom at netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_BASE_H
+#define __EDMINIV2_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __EDMINIV2_BASE_H */
diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
index 8d738c1..320e2ca 100644
--- a/drivers/net/egiga.c
+++ b/drivers/net/egiga.c
@@ -37,6 +37,8 @@
#include <asm/byteorder.h>
#if defined (CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#elif defined CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
#endif
#include "egiga.h"
@@ -273,7 +275,7 @@ static void set_dram_access(struct egiga_registers *regs)
win_param.attrib = EBAR_DRAM_CS3;
break;
default:
- /* invalide bank, disable access */
+ /* invalid bank, disable access */
win_param.enable = 0;
win_param.attrib = 0;
break;
@@ -634,26 +636,6 @@ int egiga_initialize(bd_t * bis)
int devnum;
char *s;
u8 used_ports[MAX_GBE_DEVS] = CONFIG_EGIGA_PORTS;
- u32 reg;
-
-#ifdef CONFIG_EGIGA_INIT
- /*
- * Set egiga port0/1 in normal functional mode
- * This is required becasue on kirkwood by default ports are in reset mode
- * OS egiga driver may not have provision to set them in normal mode
- * and if u-boot is build without network support, network may fail at OS level
- */
-#if defined (EGIGA0_BASE)
- reg = readl(EGIGA_PSC1_REG(EGIGA0_BASE));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (EGIGA_PSC1_REG(EGIGA0_BASE)));
-#endif
-#if defined (EGIGA1_BASE)
- reg = readl(EGIGA_PSC1_REG(EGIGA1_BASE));
- reg &= ~(1 << 4); /* Clear PortReset Bit */
- writel(reg, (EGIGA_PSC1_REG(EGIGA1_BASE)));
-#endif
-#endif
for (devnum = 0; devnum < MAX_GBE_DEVS; devnum++) {
/*skip if port is configured not to use */
diff --git a/drivers/net/egiga.h b/drivers/net/egiga.h
index f758d3c..89ac519 100644
--- a/drivers/net/egiga.h
+++ b/drivers/net/egiga.h
@@ -342,13 +342,13 @@
/* structures represents Controller registers */
struct egiga_barsz {
- u32 bar;
- u32 size;
+ volatile u32 bar;
+ volatile u32 size;
};
struct egiga_rxcdp {
- struct egiga_rxdesc *rxcdp;
- u32 rxcdp_pad[3];
+ volatile struct egiga_rxdesc *rxcdp;
+ volatile u32 rxcdp_pad[3];
};
struct egiga_tqx {
@@ -359,91 +359,91 @@ struct egiga_tqx {
};
struct egiga_registers {
- u32 phyadr;
- u32 smi;
- u32 euda;
- u32 eudid;
- u8 pad1[0x080 - 0x00c - 4];
- u32 euic;
- u32 euim;
- u8 pad2[0x094 - 0x084 - 4];
- u32 euea;
- u32 euiae;
- u8 pad3[0x0b0 - 0x098 - 4];
- u32 euc;
- u8 pad3a[0x200 - 0x0b0 - 4];
- struct egiga_barsz barsz[6];
- u8 pad4[0x280 - 0x22c - 4];
- u32 ha_remap[4];
- u32 bare;
- u32 epap;
- u8 pad5[0x400 - 0x294 - 4];
- u32 pxc;
- u32 pxcx;
- u32 mii_ser_params;
- u8 pad6[0x410 - 0x408 - 4];
- u32 evlane;
- u32 macal;
- u32 macah;
- u32 sdc;
- u32 dscp[7];
- u32 psc0;
- u32 vpt2p;
- u32 ps0;
- u32 tqc;
- u32 psc1;
- u32 ps1;
- u32 mrvl_header;
- u8 pad7[0x460 - 0x454 - 4];
- u32 ic;
- u32 ice;
- u32 pim;
- u32 peim;
- u8 pad8[0x474 - 0x46c - 4];
- u32 pxtfut;
- u32 pad9;
- u32 pxmfs;
- u32 pad10;
- u32 pxdfc;
- u32 pxofc;
- u8 pad11[0x494 - 0x488 - 4];
- u32 peuiae;
- u8 pad12[0x4bc - 0x494 - 4];
- u32 eth_type_prio;
- u8 pad13[0x4dc - 0x4bc - 4];
- u32 tqfpc;
- u32 pttbrc;
- u32 tqc1;
- u32 pmtu;
- u32 pmtbs;
- u8 pad14[0x60c - 0x4ec - 4];
- struct egiga_rxcdp rxcdp[7];
- struct egiga_rxdesc *rxcdp7;
- u32 rqc;
- struct egiga_txdesc *tcsdp;
- u8 pad15[0x6c0 - 0x684 - 4];
- struct egiga_txdesc *tcqdp[8];
- u8 pad16[0x700 - 0x6dc - 4];
- struct egiga_tqx tqx[8];
- u32 pttbc;
- u8 pad17[0x7a8 - 0x780 - 4];
- u32 tqxipg0;
- u32 pad18[3];
- u32 tqxipg1;
- u8 pad19[0x7c0 - 0x7b8 - 4];
- u32 hitkninlopkt;
- u32 hitkninasyncpkt;
- u32 lotkninasyncpkt;
- u32 pad20;
- u32 ts;
- u8 pad21[0x3000 - 0x27d0 - 4];
- u32 pad20_1[32]; /* mib counter registes */
- u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
- u32 dfsmt[64];
- u32 dfomt[64];
- u32 dfut[4];
- u8 pad23[0xe20c0 - 0x7360c - 4];
- u32 pmbus_top_arbiter;
+ volatile u32 phyadr;
+ volatile u32 smi;
+ volatile u32 euda;
+ volatile u32 eudid;
+ volatile u8 pad1[0x080 - 0x00c - 4];
+ volatile u32 euic;
+ volatile u32 euim;
+ volatile u8 pad2[0x094 - 0x084 - 4];
+ volatile u32 euea;
+ volatile u32 euiae;
+ volatile u8 pad3[0x0b0 - 0x098 - 4];
+ volatile u32 euc;
+ volatile u8 pad3a[0x200 - 0x0b0 - 4];
+ volatile struct egiga_barsz barsz[6];
+ volatile u8 pad4[0x280 - 0x22c - 4];
+ volatile u32 ha_remap[4];
+ volatile u32 bare;
+ volatile u32 epap;
+ volatile u8 pad5[0x400 - 0x294 - 4];
+ volatile u32 pxc;
+ volatile u32 pxcx;
+ volatile u32 mii_ser_params;
+ volatile u8 pad6[0x410 - 0x408 - 4];
+ volatile u32 evlane;
+ volatile u32 macal;
+ volatile u32 macah;
+ volatile u32 sdc;
+ volatile u32 dscp[7];
+ volatile u32 psc0;
+ volatile u32 vpt2p;
+ volatile u32 ps0;
+ volatile u32 tqc;
+ volatile u32 psc1;
+ volatile u32 ps1;
+ volatile u32 mrvl_header;
+ volatile u8 pad7[0x460 - 0x454 - 4];
+ volatile u32 ic;
+ volatile u32 ice;
+ volatile u32 pim;
+ volatile u32 peim;
+ volatile u8 pad8[0x474 - 0x46c - 4];
+ volatile u32 pxtfut;
+ volatile u32 pad9;
+ volatile u32 pxmfs;
+ volatile u32 pad10;
+ volatile u32 pxdfc;
+ volatile u32 pxofc;
+ volatile u8 pad11[0x494 - 0x488 - 4];
+ volatile u32 peuiae;
+ volatile u8 pad12[0x4bc - 0x494 - 4];
+ volatile u32 eth_type_prio;
+ volatile u8 pad13[0x4dc - 0x4bc - 4];
+ volatile u32 tqfpc;
+ volatile u32 pttbrc;
+ volatile u32 tqc1;
+ volatile u32 pmtu;
+ volatile u32 pmtbs;
+ volatile u8 pad14[0x60c - 0x4ec - 4];
+ volatile struct egiga_rxcdp rxcdp[7];
+ volatile struct egiga_rxdesc *rxcdp7;
+ volatile u32 rqc;
+ volatile struct egiga_txdesc *tcsdp;
+ volatile u8 pad15[0x6c0 - 0x684 - 4];
+ volatile struct egiga_txdesc *tcqdp[8];
+ volatile u8 pad16[0x700 - 0x6dc - 4];
+ volatile struct egiga_tqx tqx[8];
+ volatile u32 pttbc;
+ volatile u8 pad17[0x7a8 - 0x780 - 4];
+ volatile u32 tqxipg0;
+ volatile u32 pad18[3];
+ volatile u32 tqxipg1;
+ volatile u8 pad19[0x7c0 - 0x7b8 - 4];
+ volatile u32 hitkninlopkt;
+ volatile u32 hitkninasyncpkt;
+ volatile u32 lotkninasyncpkt;
+ volatile u32 pad20;
+ volatile u32 ts;
+ volatile u8 pad21[0x3000 - 0x27d0 - 4];
+ volatile u32 pad20_1[32]; /* mib counter registes */
+ volatile u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
+ volatile u32 dfsmt[64];
+ volatile u32 dfomt[64];
+ volatile u32 dfut[4];
+ volatile u8 pad23[0xe20c0 - 0x7360c - 4];
+ volatile u32 pmbus_top_arbiter;
};
/* structures/enums needed by driver */
@@ -476,19 +476,19 @@ struct egiga_winparam {
};
struct egiga_rxdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 buf_size; /* Buffer size */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+ volatile u32 cmd_sts; /* Descriptor command status */
+ volatile u16 buf_size; /* Buffer size */
+ volatile u16 byte_cnt; /* Descriptor buffer byte count */
+ volatile u8 *buf_ptr; /* Descriptor buffer pointer */
+ volatile struct egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct egiga_txdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 l4i_chk; /* CPU provided TCP Checksum */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer ptr */
- struct egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
+ volatile u32 cmd_sts; /* Descriptor command status */
+ volatile u16 l4i_chk; /* CPU provided TCP Checksum */
+ volatile u16 byte_cnt; /* Descriptor buffer byte count */
+ volatile u8 *buf_ptr; /* Descriptor buffer ptr */
+ volatile struct egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index c3d95a0..69253dc 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -60,7 +60,7 @@
#define ORION5X_MPP0_7 0x00000003
#define ORION5X_MPP8_15 0x55550000
-#define ORION5X_MPP16_23 0x00000000
+#define ORION5X_MPP16_23 0x00005555
/*
* Board-specific values for Orion5x GPIO low level init:
@@ -110,6 +110,14 @@
#define CONFIG_SYS_FLASH_SECTSZ \
{16384, 8192, 8192, 32768, \
65536, 65536, 65536, 65536, 65536, 65536, 65536}
+/*
+ * Ethernet
+ */
+
+#define CONFIG_EGIGA /* Enable Egiga Gbe Controller Driver */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
@@ -131,12 +139,20 @@
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
-/*
- * Disabling some default commands for staggered bring-up
- */
-#undef CONFIG_CMD_BOOTD /* no bootd since no net */
-#undef CONFIG_CMD_NET /* no net since no eth */
-#undef CONFIG_CMD_NFS /* no NFS since no net */
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#endif
/*
* Environment variables configurations
@@ -169,4 +185,6 @@
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
+
#endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 367bfb1..3015fc5 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index 6280d3d..489d34f 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -47,7 +47,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
index 60453b3..951e66d 100644
--- a/include/configs/mv88f6281gtw_ge.h
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index 3282d2d..540ee83 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -47,7 +47,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3c34d7b..10882a6 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index dc9fa95..13b4708 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -42,7 +42,7 @@
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
-#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
/*
--
1.6.4.4
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