[U-Boot] IRQ in realmode and sleep()

[Reinhard Arlt]

Hello,

the data cache is disabled on the CPCI750 board for the SDRAM by the 
DBAT entry for the SDRAM, but the data cache is enabled for most 
74xx_7xx boards in

cpu/74xx_7xx/start.S together with the translation.

The decrementer irq is executed in real mode with translation disabled.

Now in the irq routine, the processor writes the data into the cache, 
and the sleep() reads directly from RAM, and do not see the timer running.

A good solution would be to have translation on for the irq's too, but a 
simple solution is to put an '#if !(defined CPCI750)' around the 
routine, that enables the l1 data cache.

I am not shure, if the problem with the sleep() (and the missing 
timeouts in the networks stack) hits other boards too.

Reinhard