[U-Boot] [PATCH V3 7/8] fec_mxc: add MX25 support
John Rigby
jcrigby at gmail.com
Tue Mar 2 17:04:11 CET 2010
I think that is a good idea but I would like to get the current change in as
is and add this change later when needed.
2010/3/2 Lv Terry-R65388 <r65388 at freescale.com>
> Hi John,
>
> I think it is better that you can add a new config, e.g.
> CONFIG_MIIGSK for MII gasket.
> Then if other i.MX platforms uses MIIGSK, we can use the config for
> it.
>
> Thanks~~
>
> Yours
> Terry
>
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]
> On Behalf Of John Rigby
> Sent: 2010年1月26日 14:13
> To: u-boot at lists.denx.de
> Cc: John Rigby; Ben Warren
> Subject: [U-Boot] [PATCH V3 7/8] fec_mxc: add MX25 support
>
> Use RMII for MX25
> Add code to init gasket that enables RMII
>
> Signed-off-by: John Rigby <jcrigby at gmail.com>
> CC: Ben Warren <biggerbadderben at gmail.com>
> ---
> drivers/net/fec_mxc.c | 31 ++++++++++++++++++++++++++++++-
> drivers/net/fec_mxc.h | 32 ++++++++++++++++++++++++++++++--
> include/asm-arm/arch-mx25/clock.h | 1 +
> 3 files changed, 61 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index
> b5619eb..f109485 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -347,6 +347,34 @@ static int fec_open(struct eth_device *edev)
> */
> writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
> &fec->eth->ecntrl);
> +#ifdef CONFIG_MX25
> + udelay(100);
> + /*
> + * setup the MII gasket for RMII mode
> + */
> +
> + /* disable the gasket */
> + writew(0, &fec->eth->miigsk_enr);
> +
> + /* wait for the gasket to be disabled */
> + while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
> + udelay(2);
> +
> + /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
> + writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
> +
> + /* re-enable the gasket */
> + writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
> +
> + /* wait until MII gasket is ready */
> + int max_loops = 10;
> + while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
> + if (--max_loops <= 0) {
> + printf("WAIT for MII Gasket ready timed out\n");
> + break;
> + }
> + }
> +#endif
>
> miiphy_wait_aneg(edev);
> miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR); @@ -498,7 +526,8
> @@ static void fec_halt(struct eth_device *dev)
> * Disable the Ethernet Controller
> * Note: this will also reset the BD index counter!
> */
> - writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
> &fec->eth->ecntrl);
> + writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
> + &fec->eth->ecntrl);
> fec->rbd_index = 0;
> fec->tbd_index = 0;
> debug("eth_halt: done\n");
> diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index
> 6cb1bfc..5d0d69d 100644
> --- a/drivers/net/fec_mxc.h
> +++ b/drivers/net/fec_mxc.h
> @@ -145,9 +145,17 @@ struct ethernet_regs {
> uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
> uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
>
> - uint32_t res14[6]; /* MBAR_ETH + 0x2E4-2FC */
> -
> + uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
> +
> +#ifdef CONFIG_MX25
> + uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
> + uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
> + uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
> + uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
> + uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
> +#else
> uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
> +#endif
> };
>
> #define FEC_IEVENT_HBERR 0x80000000
> @@ -196,6 +204,26 @@ struct ethernet_regs {
> #define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
> #define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC
> */
>
> +#ifdef CONFIG_MX25
> +/* defines for MIIGSK */
> +/* RMII frequency control: 0=50MHz, 1=5MHz */
> +#define MIIGSK_CFGR_FRCONT (1 << 6)
> +/* loopback mode */
> +#define MIIGSK_CFGR_LBMODE (1 << 4)
> +/* echo mode */
> +#define MIIGSK_CFGR_EMODE (1 << 3)
> +/* MII gasket mode field */
> +#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
> +/* MMI/7-Wire mode */
> +#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
> +/* RMII mode */
> +#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
> +/* reflects MIIGSK Enable bit (RO) */
> +#define MIIGSK_ENR_READY (1 << 2)
> +/* enable MIGSK (set by default) */
> +#define MIIGSK_ENR_EN (1 << 1)
> +#endif
> +
> /**
> * @brief Descriptor buffer alignment
> *
> diff --git a/include/asm-arm/arch-mx25/clock.h
> b/include/asm-arm/arch-mx25/clock.h
> index b0752e7..c59f588 100644
> --- a/include/asm-arm/arch-mx25/clock.h
> +++ b/include/asm-arm/arch-mx25/clock.h
> @@ -30,6 +30,7 @@ ulong imx_get_perclk(int clk); ulong
> imx_get_ahbclk(void);
>
> #define imx_get_uartclk() imx_get_perclk(15)
> +#define imx_get_fecclk() (imx_get_ahbclk()/2)
>
>
> #endif /* __ASM_ARCH_CLOCK_H */
> --
> 1.6.4.2.236.gf324c
>
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