[U-Boot] u-boot-imx51 NAND flash Uncorrectable ECC Error

[Navaneethan P]

Hi all!

Thanks a lot for all.
Finally it happens to be a hardware problem.
It is working fine with the new hardware board.
We don't have any reason why it was not working with the older board.
Perhaps, the chip might have gone bad.

Thank you very much to all....! :)

Now, we have written some smaller jffs2 image (128K) & successfully 
mounted (ofcourse with some warnings).

When we write the whole root file system (16MB), it is giving the 
following warnings & in the mounted directory, no files are seen.

JFFS2 doesn't use OOB
jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000000: 
0xd5ba in
stead (several such errors).
Further such events for this erase block will not be printed
Old JFFS2 bitmask found at 0x00019d64
You cannot use older JFFS2 filesystems with newer kernels
Empty flash at 0x0001f7fc ends at 0x0001f800

Has any body else faced these kind of problem? Since the people who have 
worked in u-boot, might also have worked in kernel.
So that i am posting this query here.

Anway, Thanks a lot to all the folks...! :)

Thanks & Regards,
Navaneethan P 




"Liu Hui-R64343" <r64343 at freescale.com> 
03/11/2010 04:46 PM

To
"Stefano Babic" <sbabic at denx.de>, "Navaneethan P" 
<Navaneethan.P at Lntemsys.com>
cc
<u-boot at lists.denx.de>
Subject
RE: [U-Boot] u-boot-imx51 NAND flash Uncorrectable ECC Error








BR,
Jason
 

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de 
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Stefano Babic
> Sent: 2010年3月10日 1:51
> To: Navaneethan P
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] u-boot-imx51 NAND flash Uncorrectable ECC Error
> 
> Navaneethan P wrote:
> > *
> > *Hi Stefano Babic,
> >
> 
> Hi Navaneethan,
> 
> I will kindly ask you to send your questions directly to the 
> u-boot mailing list, too.
> 
> This information can be helpful for other users of this 
> board. And you get a large number of developers who could help you.
> 
> > We are using the imx51 babbage board with external NAND flash 
> > (NAND01GR3B2C , numonyx 8 bit, 2k page size, 1Gbit, 128k 
> block size) 
> > connected.
> 
> In the patchset I provided to the ML I will not set the iomux 
> for NAND, because the babbage board (mx51evk) has no NAND at 
> all. I suppose you have configured the iomux, too. Anything 
> else you changed ?
> 
> > We are using the standard NAND driver from u-boot source 
> > (u-boot-2009.08). Initially nand read was not proper.
> > I changed the read operation from auto operation to manual 
> operation.
> 
> After that time, some patches went to the mainline for the 
> MXC NAND driver to support revision 1.1 of the Freescale's 
> NAND controller. As I can see, the MX51 has version 1.1 as 
> the MX25 (not really checked, but it seems so).

MX51 NFC(nand flash controler) is not the MX25 like. There is
Big difference.MX51 support auto-mode and the register is 32-bit width
While MX25 not that.

> 
> I think it makes sense if you align your code with the actual 
> u-boot top of tree, that you can find on git.denx.de
> 
> > 
> > Now, write, read, and erase are seems to be working fine.
> > 
> > When we write the filesystem/linux kernel, there seems to be a byte 
> > error. Means, one byte mismatch between the written data & 
> read data.
> > 
> > Example, (written data != read data)
> > 
> > byte at 0x90800457 (0xff) != byte at 0x90c00457 (0x92) byte at 
> > 0x90800458 (0x92) != byte at 0x90c00458 (0xff) byte at 0x9080045a 
> > (0xff) != byte at 0x90c0045a (0xea) byte at 0x9080045a 
> (0xff) != byte 
> > at 0x90c0045a (0xea) byte at 0x9080045b (0xea) != byte at 
> 0x90c0045b 
> > (0x4f) byte at 0x9080045c (0x4f) != byte at 0x90c0045c 
> (0x00) byte at 
> > 0x9080045e (0x00) != byte at 0x90c0045e (0xea)
> > 
> > When we read the linux kernel, it is giving Uncorrectable 
> RS ECC Error

Kernel print out Uncorrectable  RS ECC Error means the data corruption and 
the HW ECC of NFC can't correct it.
It may due to the NAND driver. BTW, please make sure erase the block first 
when you operate on MLC nand flash since
NOP=1. 

> 
> Ok, this is understandable, if the values read are not what 
> you wanted to write. It seems each byte is written at the 
> next address. I have not yet an explanation, but maybe 
> someone else in the ML can help.
> 
> Regards,
> Stefano Babic
> 
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