[U-Boot] [PATCH V2 3/7] Add memory test feature for mpc85xx POST.

[Wolfgang Denk]

Dear York Sun,

In message <1285691891-32700-3-git-send-email-yorksun at freescale.com> you wrote:
> The memory test is performed after DDR initialization when U-boot stills runs
> in flash and cache. Whole memory can be tested. It is mapped 2GB at a time
> using a sliding TLB window. After the testing, DDR is remapped with up to 2GB
> memory from the lowest address as normal.
> 
> If memory test fails, DDR DIMM SPD and DDR controller registers are dumped.
> 
> Signed-off-by: York Sun <yorksun at freescale.com>

Please see previous comments about empty lines etc. to make to code
more readable.

Also, please add some comments to explain what you are actually doing.

> +Memory testing options for mpc85xx
> +==================================
> +1. Memory test can be done one U-boot prompt comes up using mtest, or

s/one/once/ ?

> +2. Memory test can be done with Power-On-Self-Test function, activated at compile time.
> +
> +   In order to enable the POST memory test, CONFIG_POST needs to be
> +   defined in board configuraiton header file. By default, POST memory test performs
> +   a fast test. A slow test can be enabled by changing the flag at compiling time.
> +   To test memory bigger than 2GB, 36BIT support is needed. Memory is tested within
> +   a 2GB window. TLBs are used to map the virtual 2GB window to physical address
> +   so that all physical memory can be tested.

Lines too long.


Best regards,

Wolfgang Denk

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