[U-Boot] [PATCH v7 05/10] nds32/ag101: lowlevel_init.S of ag101

[Macpaul Lin]

HI Wolfgang and all,

2011/4/7 Macpaul Lin <macpaul at andestech.com>:
> lowlevel_init.S is a peripheral initial procedure of ag101.
> It configures onboard dram, clock, and power settings.
> It also prepars the dram environment before moving u-boot
> from rom and flash into dram.
>

I'm so sorry there is really a need to setup the timing related parameters
in assembly because the poor of hardware design.
Without the correct timing parameters, we cannot read/write dram.
Even we couldn't use it  to store the initial stack,

I have posted the spec of related timing parameter of memory
controller as following
(which is connected to the first bank of DRAM).
Hope you can understand the problem from the hardware (register) spec.

example:
FTSMC020_BANK0_TPR (control the dram)
value: 0x00151151

20   , RBE, set to (b'1), R/W Read byte-enable.
       If this bit is set to '1’, byte-enable will be pulled LOW when read.
       Otherwise, byte-enable will be pulled LOW only for write operation.
19-18, AST, R/W, set to (b'01),
       Address setup time.
       This register specifies the latency needed to assert
chip-enable after address assertion.
17-16, CTW, R/W, set to (b'01),
       Chip-select to write-enable delay.
       This register specifies the latency needed to assert
write-enable after chip-enable assertion.
15-12, AT1, R/W, set to (b'0001),
       Access time 1.
       This register specifies the latency to latch (read) or change
data (write)
       after write-enable assertion when general asynchronous device
is specified.
       The value must be larger than zero. Setting this register to zero is
       acceptable but the behavior will be un-predictable.
       If device is specified as burst ROM, this register indicates
the read/write latency of first data.
       If BNK_TYPE1 is set as ‘1’ (synchronous devices),
       this register indicates the depth of late-write and the maximum
value of this value is 2 (value exceeding 2 will be reset to zero).
11-10, Reserved, set to (b'00)
       Writing data to this register takes no effect and zero will be
returned when read.
9-8, AT2, R/W, set to (b'01)
       Access time 2.
       This register specifies the latency needed to latch the burst read data.
       This register is only used when device type is specified as burst ROM.
7-6, WTC, R/W, set to (b'01)
       Write-enable to chip-select delay.
       This register specifies the latency needed to de-assert
chip-enable after write-enable de-assertion.
5-4, AHT, R/W, set to (b'01)
       Address hold time.
       This register specifies the latency needed to de-assert address
after chip-select de-assertion.
3-0, TRNA, R/W, set to (b'0001)
       Turn-around time. This register specifies the latency needed to
re-drive data bus.