[U-Boot] [PATCH 2/2] cpu9260: update board support

[Reinhard Meyer]

Dear Eric Bénard,
> - update to new relocation code
> - switch to boards.cfg
> - get rid of LEGACY (still a little hack in .h to compile)
> - add nand boot configuration
> - boot tested for the following configurations :
> 	9260 (64MB RAM & nor boot)
> 	9260_nand (64MB RAM & nand boot)
> 	9G20_128M (128MB RAM & nor boot)
> 	9G20_nand_128M (128MB RAM & nand boot)
> 	(nor boot is using lowlevel init)
> 
> Signed-off-by: Eric Bénard <eric at eukrea.com>
> ---
>  board/eukrea/cpu9260/config.mk |    1 -
>  board/eukrea/cpu9260/cpu9260.c |  161 +++++++++++++++++----------------------
>  board/eukrea/cpu9260/led.c     |   36 +++++----
>  boards.cfg                     |    8 ++
>  include/configs/cpu9260.h      |  164 +++++++++++++++++++++++++++------------
>  5 files changed, 209 insertions(+), 161 deletions(-)
>  delete mode 100644 board/eukrea/cpu9260/config.mk

...

> diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
> index d239423..09dc03c 100644
> --- a/include/configs/cpu9260.h
> +++ b/include/configs/cpu9260.h
> @@ -31,9 +31,11 @@
>  #ifndef __CONFIG_H
>  #define __CONFIG_H
>  
> -#define CONFIG_AT91_LEGACY
> +/* to be removed once maemory-map.h is fixed */

That would be "memory-map.h".
However memory-map.h does not exist anymore.

> +#define AT91_BASE_SYS	0xffffe800
> +#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)

Above two defines should nowhere be needed anymore.
Please fix globally.

> -#define CONFIG_DISPLAY_CPUINFO	1
> +#include <asm/sizes.h>
>  
>  #define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
>  #define CONFIG_SYS_HZ		1000
> @@ -54,13 +56,23 @@
>  #error "Unknown board"
>  #endif
>  
> +#define CONFIG_AT91FAMILY
>  #define CONFIG_ARCH_CPU_INIT
>  #undef CONFIG_USE_IRQ
> +#define CONFIG_DISPLAY_CPUINFO		1
> +#define CONFIG_BOARD_EARLY_INIT_F	1
>  
>  #define CONFIG_CMDLINE_TAG		1
>  #define CONFIG_SETUP_MEMORY_TAGS 	1
>  #define CONFIG_INITRD_TAG		1

Please no "1" anymore for just defines, unless the value 1 is really used as a value.

>  
> +#if defined(CONFIG_NANDBOOT)
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_SYS_TEXT_BASE           0x23f00000
> +#else
> +#define CONFIG_SYS_TEXT_BASE           0x00000000
> +#endif
> +
>  /* clocks */
>  #if defined(CONFIG_CPU9G20)
>  #define MASTER_PLL_DIV		0x01
> @@ -113,8 +125,8 @@
>  
>  /* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
>  #define CONFIG_SYS_MATRIX_EBICSA_VAL		\
> -       (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC |\
> -       AT91_MATRIX_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_VDDIOMSEL)
> +		(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
> +		AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
>  
>  /* SDRAM */
>  /* SDRAMC_MR Mode register */
> @@ -199,51 +211,52 @@
>  /* setup SMC0, CS0 (NOR Flash) - 16-bit */
>  #if defined(CONFIG_CPU9G20)
>  #define CONFIG_SYS_SMC0_SETUP0_VAL					\
> -		(AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |	\
> -		 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
> +		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
> +		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
>  #define CONFIG_SYS_SMC0_PULSE0_VAL					\
> -		(AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(8) |	\
> -		 AT91_SMC_NRDPULSE_(14) | AT91_SMC_NCS_RDPULSE_(14))
> +		(AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |	\
> +		 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
>  #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
> -		(AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(14))
> +		(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
>  #define CONFIG_SYS_SMC0_MODE0_VAL				\
> -		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
> -		 AT91_SMC_DBW_16 |				\
> -		 AT91_SMC_TDFMODE |				\
> -		 AT91_SMC_TDF_(3))
> +		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
> +		 AT91_SMC_MODE_DBW_16 |				\
> +		 AT91_SMC_MODE_TDF |				\
> +		 AT91_SMC_MODE_TDF_CYCLE(3))
>  #elif defined(CONFIG_CPU9260)
>  #define CONFIG_SYS_SMC0_SETUP0_VAL					\
> -		(AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |	\
> -		 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0))
> +		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
> +		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
>  #define CONFIG_SYS_SMC0_PULSE0_VAL					\
> -		(AT91_SMC_NWEPULSE_(6) | AT91_SMC_NCS_WRPULSE_(6) |	\
> -		 AT91_SMC_NRDPULSE_(10) | AT91_SMC_NCS_RDPULSE_(10))
> +		(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |	\
> +		 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
>  #define CONFIG_SYS_SMC0_CYCLE0_VAL	\
> -		(AT91_SMC_NWECYCLE_(6) | AT91_SMC_NRDCYCLE_(10))
> +		(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
>  #define CONFIG_SYS_SMC0_MODE0_VAL				\
> -		(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |	\
> -		 AT91_SMC_DBW_16 |				\
> -		 AT91_SMC_TDFMODE |				\
> -		 AT91_SMC_TDF_(2))
> +		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
> +		 AT91_SMC_MODE_DBW_16 |				\
> +		 AT91_SMC_MODE_TDF |				\
> +		 AT91_SMC_MODE_TDF_CYCLE(2))
>  #endif
>  
>  /* user reset enable */
>  #define CONFIG_SYS_RSTC_RMR_VAL			\
>  		(AT91_RSTC_KEY |		\
> -		AT91_RSTC_PROCRST |		\
> -		AT91_RSTC_RSTTYP_WAKEUP |	\
> -		AT91_RSTC_RSTTYP_WATCHDOG)
> +		AT91_RSTC_CR_PROCRST |		\
> +		AT91_RSTC_MR_ERSTL(1) |	\
> +		AT91_RSTC_MR_ERSTL(2))
>  
>  /* Disable Watchdog */
>  #define CONFIG_SYS_WDTC_WDMR_VAL				\
> -		(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |	\
> -		 AT91_WDT_WDV |					\
> -		 AT91_WDT_WDDIS |				\
> -		 AT91_WDT_WDD)
> +		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
> +		 AT91_WDT_MR_WDV(0xfff) |			\
> +		 AT91_WDT_MR_WDDIS |				\
> +		 AT91_WDT_MR_WDD(0xfff))
>  
>  /*
>   * Hardware drivers
>   */
> +#define CONFIG_AT91SAM9_WATCHDOG	1
>  #define CONFIG_AT91_GPIO	1
>  #define CONFIG_ATMEL_USART	1
>  #undef CONFIG_USART0
> @@ -276,15 +289,16 @@
>  #define CONFIG_CMD_NAND		1
>  #define CONFIG_CMD_USB		1
>  #define CONFIG_CMD_FAT		1
> +#define CONFIG_CMD_MII		1
>  
>  /* SDRAM */
>  #define CONFIG_NR_DRAM_BANKS	1
> -#define PHYS_SDRAM		0x20000000
> +#define CONFIG_SYS_SDRAM_BASE		0x20000000
>  #if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
> -#define PHYS_SDRAM_SIZE		0x08000000	/* 128 MB */
> +#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
>  #define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_128MB
>  #else
> -#define PHYS_SDRAM_SIZE		0x04000000	/* 64 MB */
> +#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
>  #define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_64MB
>  #endif
>  
> @@ -294,12 +308,15 @@
>  #define CONFIG_SYS_MAX_NAND_DEVICE		1
>  #define CONFIG_SYS_NAND_BASE			0x40000000
>  #define CONFIG_SYS_NAND_DBW_8			1
> -#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13
> -#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
> +#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTC, 13
> +#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
>  #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
>  #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
>  
>  /* NOR flash */
> +#if defined(CONFIG_NANDBOOT)
> +#define CONFIG_SYS_NO_FLASH			1
> +#else
>  #define CONFIG_SYS_FLASH_CFI			1
>  #define CONFIG_FLASH_CFI_DRIVER			1
>  #define PHYS_FLASH_1				0x10000000
> @@ -314,11 +331,11 @@
>  #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
>  #define CONFIG_SYS_FLASH_PROTECTION		1
>  #define CONFIG_SYS_MONITOR_BASE			PHYS_FLASH_1
> +#endif
>  
>  /* Ethernet */
>  #define CONFIG_MACB				1
>  #define CONFIG_RMII				1
> -#define CONFIG_RESET_PHY_R			1
>  #define CONFIG_NET_MULTI			1
>  #define CONFIG_NET_RETRY_COUNT			20
>  #define CONFIG_MACB_SEARCH_PHY			1
> @@ -350,10 +367,10 @@
>  /* Optional value */
>  #define STATUS_LED_BOOT				STATUS_LED_BIT
>  
> -#define CONFIG_RED_LED				AT91_PIN_PC11
> -#define CONFIG_GREEN_LED			AT91_PIN_PC12
> -#define CONFIG_YELLOW_LED			AT91_PIN_PC7
> -#define CONFIG_BLUE_LED				AT91_PIN_PC9
> +#define CONFIG_RED_LED				AT91_PIO_PORTC, 11
> +#define CONFIG_GREEN_LED			AT91_PIO_PORTC, 12
> +#define CONFIG_YELLOW_LED			AT91_PIO_PORTC, 7
> +#define CONFIG_BLUE_LED				AT91_PIO_PORTC, 9
>  
>  /* USB */
>  #define CONFIG_USB_ATMEL			1
> @@ -361,17 +378,33 @@
>  #define CONFIG_DOS_PARTITION			1
>  #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
>  #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
> +#if defined(CONFIG_CPU9G20)
> +#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g20"
> +#elif defined(CONFIG_CPU9260)
>  #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
> +#endif
>  #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
>  #define CONFIG_USB_STORAGE			1
>  
>  #define CONFIG_SYS_LOAD_ADDR			0x21000000
>  
> -#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
> -#define CONFIG_SYS_MEMTEST_END			0x21e00000
> +#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END			\
> +	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_512K)
>  
> -#undef CONFIG_SYS_USE_NANDFLASH
> +#if defined(CONFIG_NANDBOOT)
> +#define CONFIG_SYS_USE_NANDFLASH		1
> +#undef CONFIG_SYS_USE_FLASH
> +#else
>  #define CONFIG_SYS_USE_FLASH			1
> +#undef CONFIG_SYS_USE_NANDFLASH
> +#endif
> +
> +#if defined(CONFIG_CPU9G20)
> +#define CONFIG_SYS_BASEDIR	"cpu9G20"
> +#elif defined(CONFIG_CPU9260)
> +#define CONFIG_SYS_BASEDIR	"cpu9260"
> +#endif
>  
>  #if defined(CONFIG_SYS_USE_FLASH)
>  #define CONFIG_ENV_IS_IN_FLASH		1
> @@ -382,7 +415,7 @@
>  
>  #define CONFIG_BOOTCOMMAND		"run flashboot"
>  
> -#define MTDIDS_DEFAULT	 	"nor0=physmap-flash.0,nand0=atmel_nand"
> +#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=atmel_nand"
>  #define MTDPARTS_DEFAULT		\
>  	"mtdparts=physmap-flash.0:"	\
>  		"256k(u-boot)ro,"	\
> @@ -393,18 +426,12 @@
>  
>  #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
>  
> -#if defined(CONFIG_CPU9G20)
> -#define CONFIG_SYS_BASEDIR	"cpu9G20"
> -#elif defined(CONFIG_CPU9260)
> -#define CONFIG_SYS_BASEDIR	"cpu9260"
> -#endif
> -
>  #define CONFIG_EXTRA_ENV_SETTINGS				\
>  	"mtdids=" MTDIDS_DEFAULT "\0"				\
>  	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
>  	"partition=nand0,0\0"					\
>  	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
> -	"ramboot=tftpboot 0x22000000 cpu9260/uImage;"		\
> +	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
>  		"run ramargs;bootm 22000000\0"			\
>  	"flashboot=run ramargs;bootm 0x10060000\0"		\
>  	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
> @@ -421,6 +448,38 @@
>  		"0x10220000 0x13ffffff;cp.b 0x24000000 "	\
>  		"0x10220000 $(filesize)\0" \
>  	""
> +#elif defined(CONFIG_NANDBOOT)
> +#define CONFIG_ENV_IS_IN_NAND		1
> +#define CONFIG_ENV_OFFSET		0x60000
> +#define CONFIG_ENV_OFFSET_REDUND	0x80000
> +#define CONFIG_ENV_SECT_SIZE		0x20000
> +#define	CONFIG_ENV_SIZE			0x20000
> +#define CONFIG_ENV_OVERWRITE		1
> +
> +#define CONFIG_BOOTCOMMAND		"run flashboot"
> +
> +#define MTDIDS_DEFAULT		"nand0=atmel_nand"
> +#define MTDPARTS_DEFAULT		\
> +	"mtdparts=atmel_nand:"		\
> +		"128k(bootstrap)ro,"	\
> +		"256k(u-boot)ro,"	\
> +		"128k(u-boot-env)ro,"	\
> +		"128k(u-boot-env2)ro,"	\
> +		"2M(kernel),"	\
> +		"-(rootfs)"
> +
> +#define CONFIG_BOOTARGS "root=/dev/mtdblock5 rootfstype=ubifs "
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS				\
> +	"mtdids=" MTDIDS_DEFAULT "\0"				\
> +	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
> +	"partition=nand0,5\0"					\
> +	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
> +	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
> +		"run ramargs;bootm 22000000\0"			\
> +	"flashboot=run ramargs; nand read 0x22000000 0xA0000 "	\
> +		"0x200000; bootm 0x22000000\0"			\
> +	"basedir=" CONFIG_SYS_BASEDIR "\0"
>  #endif
>  
>  #define CONFIG_BAUDRATE			115200
> @@ -446,7 +505,10 @@
>  #define CONFIG_SYS_MALLOC_LEN		\
>  		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
>  
> -#define CONFIG_STACKSIZE		(32 * 1024)
> +#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + SZ_4K - \
> +				GENERATED_GBL_DATA_SIZE)
> +
> +#define CONFIG_STACKSIZE		SZ_32K

No SZ_ maxros anymore. Please fix globally.

>  
>  #if defined(CONFIG_USE_IRQ)
>  #error CONFIG_USE_IRQ not supported

Best Regards,

Reinhard