[U-Boot] [PATCH v3] fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC

[Wolfgang Denk]

Dear Kyle Moffett,

In message <1300202627-7245-1-git-send-email-Kyle.D.Moffett at boeing.com> you wrote:
> The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
> integer divide operations to convert between nanoseconds and DDR clock
> cycles given arbitrary DDR clock frequencies.
...
> +/* To avoid 64-bit full-divides, we factor this here */
> +#define ULL_2e12 2000000000000ULL
> +#define UL_5pow12 244140625UL
> +#define UL_2pow13 (1UL << 13)
> +
> +#define ULL_8Fs 0xFFFFFFFFULL

Unfortunately this is already in mainline.  Can you please send a
cleanup patch to fix the CamelCaps macro names?

Thanks.

Best regards,

Wolfgang Denk

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