[U-Boot] [PATCH V1 1/1] MX5: Keep L2 cache enabled before jump to kernel

[Jason Liu]

Hi, Stefano,

2011/4/15 Stefano Babic <sbabic at denx.de>:
> On 04/13/2011 03:25 PM, Jason Liu wrote:
>
> Hi Jason,
>
>> Currently, Linux kernel does not do any L2 cache enable
>> Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot
>> before Jump to the Linux Kernel and thus L2 cache can be
>> effectively used in Linux Kernel.
>
> If the cache is not active in the kernel for MX5, this should be fixed
> in the kernel for this architecture. Normally, cache is activated inside
> the kernel itself, as I cann see for other architectures and other ARMV7
> processors (omap)

Here the cache is L2 cache. I have observed that if uboot does not enable it,
then L2 cache will not get enabled through current ARM linux core code.

And for the uboot itself it provide the following code in cpu.c to
enable L2 cache
before jump to linux kernel, and this code maybe implemented by omap guys:
If linux kernel already enabled it, then there is no need for the L2
related code here?

int cleanup_before_linux(void)
{
        unsigned int i;

        /*
         * this function is called just before we call linux
         * it prepares the processor for linux
         *
         * we turn off caches etc ...
         */
        disable_interrupts();

        /* turn off I/D-cache */
        icache_disable();
        dcache_disable();

        /* invalidate I-cache */
        cache_flush();

#ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
        l2_cache_disable();
        /* invalidate L2 cache also */
        invalidate_dcache(get_device_type());
#endif
        i = 0;
        /* mem barrier to sync up things */
        asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));

#ifndef CONFIG_L2_OFF
        l2_cache_enable();
#endif

>
> However, if you plan to add cache support, why not add the functions to
> get the cache enabled in u-boot ?

Yes, good point.
This is my to-do task but It will need much work to make the driver work
when enable d-cache support.

>
>> +
>> +/*
>> + * Sine we did not enable D-cache in uboot,this is the
>> + * Dummy function for L2 ON to make build pass. please
>> + * Check the arch/arm/cpu/armv7/cpu.c file
>> + */
>
> This seems to me a workaround for a non clear problem (at least, not
> clear for me..) to activate the cache at the startup of the kernel.
> There are already processors in u-boot supporting the cache, and if we
> add caching functions to u-boot for i.MX5, we must implement the full
> support to have cache active in the bootloader.

Here, as the comment said, since uboot does not enable L2 cache before
it jump to linux kernel, so, this function is just the dummy function to
pass build. Take the code from arch/arm/cpu/armv7/cpu.c:
int cleanup_before_linux(void)
{
...
#ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
        l2_cache_disable();
        /* invalidate L2 cache also */
        invalidate_dcache(get_device_type());
#endif

>
>
>> +invalidate_dcache:
>> +     mov     pc, lr
>> +
>> +l2_cache_enable:
>> +     mrc     p15, 0, r0, c1, c0, 1;
>
> No registers are saved before calling this funtion ?

I don't think it needs save any register.

Jason

>
> Best regards,
> Stefano Babic
>
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