[U-Boot] [PATCH 1/4] powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005

[Kumar Gala]

On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote:

> From: Timur Tabi <timur at freescale.com>
> 
> SerDes PLL bandwidth default setting is incorrect when no lanes are
> configured as PCI Express.
> 
> Signed-off-by: Timur Tabi <timur at freescale.com>
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c         |    3 ++
> arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c |   48 +++++++++++++++++++++++++
> arch/powerpc/include/asm/config_mpc85xx.h     |    1 +
> 3 files changed, 52 insertions(+), 0 deletions(-)

applied to 85xx

- k