[U-Boot] [PATCH] powerpc/p4080: Add support for secure boot flow on CoreNet Based QorIQ chips

[Wolfgang Denk]

Dear Kumar Gala,

In message <1302373725-21799-1-git-send-email-galak at kernel.crashing.org> you wrote:
...
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> index 6f256cf..aafb007 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> @@ -239,6 +239,13 @@ void cpu_init_f (void)
>  	disable_tlb(14);
>  	disable_tlb(15);
>  
> +#ifdef CONFIG_SYS_ESBC_FLASH
> +	/* Disable the LAW created for NOR flash by the PBI commands */
> +	struct law_entry law = find_law(CONFIG_SYS_PBI_FLASH_BASE);

NAK.  We do not allow variable declaratios in the middle of the code.

> +#if defined(CONFIG_SECURE_BOOT)
> +/* Disable the TLBs created by ISBC */
> +	for (i = CONFIG_SYS_ISBC_START_TLB;

The comment should be indented as the following code.

> +#ifdef CONFIG_SECURE_BOOT
> +	/* ISBC uses L2 as stack.
> +	Disable L2 cache here so that u-boot can enable it later
> +	as part of it's normal flow
> +	*/

Incorrect multiline comment style.  Please fix globally.

> +	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
> +	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l

Lines too long.  Please fix globally.

...
> --- a/include/configs/corenet_ds.h
> +++ b/include/configs/corenet_ds.h
> @@ -607,4 +607,8 @@
>  
>  #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
>  
> +#ifdef CONFIG_SECURE_BOOT
> +#include <asm/fsl_secure_boot.h>
> +#endif

Is this #ifdef really needed ?

Best regards,

Wolfgang Denk

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