[U-Boot] [PATCH 11/12] da850: modifications for Logic PD Rev.3 AM18xx EVM

[Wolfgang Denk]

Dear nagabhushana.netagunte at ti.com,

In message <1312299792-16415-12-git-send-email-nagabhushana.netagunte at ti.com> you wrote:
> From: Nagabhushana Netagunte <nagabhushana.netagunte at ti.com>
> 
> AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
> NOR to work on Rev.3 EVM. When GP0[11] is low,
> the SD0 interface will not work, but NOR flash will.
> 
> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj at ti.com>
> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte at ti.com>
> ---
>  arch/arm/include/asm/arch-davinci/hardware.h |    5 ++++-
>  board/davinci/da8xxevm/da850evm.c            |   15 +++++++++++++++
>  2 files changed, 19 insertions(+), 1 deletions(-)
...
> +#ifdef CONFIG_USE_NOR
> +	/* Set the GPIO direction as output */
> +	val = readl(GPIO_BANK0_REG_DIR_ADDR);
> +	val &= ~(0x01 << 11);
> +	writel(val, GPIO_BANK0_REG_DIR_ADDR);
> +
> +	/* Set the output as low */
> +	val = readl(GPIO_BANK0_REG_SET_ADDR);
> +	val |= (0x01 << 11);
> +	writel(val, GPIO_BANK0_REG_CLR_ADDR);
> +#endif

Please use standard clrbits / setbits macros instead.



Best regards,

Wolfgang Denk

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