[U-Boot] [PATCH 11/12] da850: modifications for Logic PD Rev.3 AM18xx EVM

[Netagunte, Nagabhushana]

Denk,
Thanks a lot for comments. I will incorporate changes suggested by you.

Regards,
Nag

On Tue, Aug 02, 2011 at 22:02:12, Wolfgang Denk wrote:
> Dear nagabhushana.netagunte at ti.com,
> 
> In message <1312299792-16415-12-git-send-email-nagabhushana.netagunte at ti.com> you wrote:
> > From: Nagabhushana Netagunte <nagabhushana.netagunte at ti.com>
> > 
> > AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on 
> > Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but 
> > NOR flash will.
> > 
> > Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj at ti.com>
> > Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte at ti.com>
> > ---
> >  arch/arm/include/asm/arch-davinci/hardware.h |    5 ++++-
> >  board/davinci/da8xxevm/da850evm.c            |   15 +++++++++++++++
> >  2 files changed, 19 insertions(+), 1 deletions(-)
> ...
> > +#ifdef CONFIG_USE_NOR
> > +	/* Set the GPIO direction as output */
> > +	val = readl(GPIO_BANK0_REG_DIR_ADDR);
> > +	val &= ~(0x01 << 11);
> > +	writel(val, GPIO_BANK0_REG_DIR_ADDR);
> > +
> > +	/* Set the output as low */
> > +	val = readl(GPIO_BANK0_REG_SET_ADDR);
> > +	val |= (0x01 << 11);
> > +	writel(val, GPIO_BANK0_REG_CLR_ADDR); #endif
> 
> Please use standard clrbits / setbits macros instead.
> 
> 
> 
> Best regards,
> 
> Wolfgang Denk
> 
> -- 
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "If that makes any sense to you, you have a big problem."
>                                   -- C. Durance, Computer Science 234
>