[U-Boot] [PATCH 5/8] AM3517 EVM: Add am3517_evm_norflash and _norflash_boot targets
Tom Rini
trini at ti.com
Tue Dec 6 16:49:39 CET 2011
These build targets will make a U-Boot that knows about the NOR
flash that can be enabled on this board (see previous commits for
details) and a U-Boot that can run from NOR flash (u-boot.bin).
When we are building to run from NOR flash we makes changes to
the default environment in order to run the system fully from
NOR flash. This results in a lot of 'noise' in terms of moving
NAND-specific config options to be in one place that we can
key off of. We also modify the bootcmd to use the flash the
user has chosen (by building for NOR, or NAND).
Signed-off-by: Tom Rini <trini at ti.com>
---
boards.cfg | 2 +
include/configs/am3517_evm.h | 142 +++++++++++++++++++++++++----------------
2 files changed, 88 insertions(+), 56 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 50f2e5f..7b0cfc5 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -187,6 +187,8 @@ igep0020 arm armv7 igep0020 isee
igep0030 arm armv7 igep0030 isee omap3
am3517_crane arm armv7 am3517crane ti omap3
am3517_evm arm armv7 am3517evm logicpd omap3
+am3517_evm_norflash arm armv7 am3517evm logicpd omap3 am3517_evm:SYS_HAS_NORFLASH
+am3517_evm_norflash_boot arm armv7 am3517evm logicpd omap3 am3517_evm:SYS_HAS_NORFLASH,SYS_BOOT_NORFLASH
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 39f1a82..8eb693a 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -147,12 +147,10 @@
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
@@ -175,19 +173,16 @@
/* NAND devices */
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
-#define CONFIG_JFFS2_NAND
-/* nand device jffs2 lives on */
-#define CONFIG_JFFS2_DEV "nand0"
-/* start of jffs2 partition */
-#define CONFIG_JFFS2_PART_OFFSET 0x680000
-#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_EXTRA_ENV_SETTINGS \
+/* Basic 'extra' env variables */
+#define EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyO2,115200n8\0" \
"mmcdev=0\0" \
@@ -203,10 +198,6 @@
"setenv bootargs ${bootargs} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
- "nandargs=run bootargs_defaults; " \
- "setenv bootargs ${bootargs} " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
@@ -214,10 +205,6 @@
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
@@ -234,10 +221,10 @@
"fi;" \
"if run loaduimage; then " \
"run mmcboot; " \
- "else run nandboot; " \
+ "else run " FLASHBOOT "; " \
"fi; " \
"fi; " \
- "else run nandboot; fi"
+ "else run " FLASHBOOT "; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
@@ -292,47 +279,81 @@
* FLASH and environment organization
*/
-/* **** PISMO SUPPORT *** */
-
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
-#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
- /* on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
-
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
-#endif
+/* General */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KiB */
+/*
+ * CFI FLASH driver setup. Please note that, first 4 blocks are of 32K and
+ * rest all blocks are 128K.
+ */
+#if defined (CONFIG_SYS_HAS_NORFLASH)
+#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_SYS_FLASH_BASE DEBUG_BASE
+#define CONFIG_SYS_FLASH_CFI /* use CFI geometry data */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster writes */
+#define CONFIG_SYS_FLASH_PROTECTION /* hardware sector protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo 'E' for empty */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI_WIDTH 2
+#define PHYS_FLASH_SIZE (8 << 20)
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#else
+/* No support for CFI flash. */
+#undef CONFIG_CMD_FLASH
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS 0
+#endif
-#define CONFIG_NAND_OMAP_GPMC
-#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
-#define CONFIG_ENV_IS_IN_NAND 1
+/* Environment location */
+#ifdef CONFIG_SYS_BOOT_NORFLASH
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
+/* NOR related env and boot */
+#define FLASHBOOT "norboot"
+#define CONFIG_EXTRA_ENV_SETTINGS EXTRA_ENV_SETTINGS \
+ "norargs=run bootargs_defaults; " \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/mtdblock3 rw " \
+ "rootfstype=jffs2\0" \
+ "norboot=echo Booting from nor ...; " \
+ "run norargs; " \
+ "bootm 0x080A0000; \0"
+/* JFFS2 */
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x400000
+#define CONFIG_JFFS2_PART_SIZE 0x400000 /* sz of jffs2 part */
+#else
+/* ENV resides in NAND */
+#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
-
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
-#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
-
-/* Flash banks JFFS2 should use */
-#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
-#define CONFIG_SYS_JFFS2_MEM_NAND
-/* use flash_info[2] */
-#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+/* NAND related env and boot */
+#define FLASHBOOT "nandboot"
+#define CONFIG_EXTRA_ENV_SETTINGS EXTRA_ENV_SETTINGS \
+ "nandargs=run bootargs_defaults; " \
+ "setenv bootargs ${bootargs} " \
+ "root=/dev/mtdblock4 rw " \
+ "rootfstype=jffs2\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 280000 500000; " \
+ "bootm ${loadaddr}\0"
+/* JFFS2 */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV "nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET 0x780000
+#define CONFIG_JFFS2_PART_SIZE 0x1f880000 /* sz of jffs2 part */
+#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
@@ -341,9 +362,12 @@
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
-/* Defines for SPL */
+/*
+ * SPL support. No need to build all of this if we are going to be
+ * booting from NOR instead.
+ */
+#ifndef CONFIG_SYS_BOOT_NORFLASH
#define CONFIG_SPL
-#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_SPL_MAX_SIZE (45 * 1024)
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
@@ -363,11 +387,12 @@
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
/* NAND boot config */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
@@ -380,19 +405,24 @@
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)
-#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+#endif
/*
+ * For NOR we need to link at where NOR is mapped at. Otherwise, we are
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
* header. That is 0x800FFFC0--0x80100000 should not be used for any
* other needs.
*/
+#ifdef CONFIG_SYS_BOOT_NORFLASH
+#define CONFIG_SYS_TEXT_BASE 0x08000000
+#else
#define CONFIG_SYS_TEXT_BASE 0x80100000
+#endif
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
-
#endif /* __CONFIG_H */
--
1.7.0.4
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