[U-Boot] [PATCH] overo: add SPL support

[Steve Sakoman]

On Wed, Dec 14, 2011 at 8:27 AM, Andreas Müller <schnitzeltony at gmx.de> wrote:
> * implemenatation based on ti beagleboard/omap3evm
> * timing data taken from x-loader
> * run-tested with overo release 0 and 1 / boot from NAND and SDcard

Thanks for doing this!

I took a quick look and only see one addition to Tom's comments.  See below.

> Signed-off-by: Andreas Müller <schnitzeltony at gmx.de>
> ---
>  arch/arm/include/asm/arch-omap3/mem.h |   27 ++++++++++++++++
>  board/overo/config.mk                 |   28 ----------------
>  board/overo/overo.c                   |   41 +++++++++++++++++++++++-
>  include/configs/omap3_overo.h         |   56 ++++++++++++++++++++++++++++++++-
>  4 files changed, 122 insertions(+), 30 deletions(-)
>  delete mode 100644 board/overo/config.mk
>
> diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
> index 5fd02d4..18998d8 100644
> --- a/arch/arm/include/asm/arch-omap3/mem.h
> +++ b/arch/arm/include/asm/arch-omap3/mem.h
> @@ -123,6 +123,33 @@ enum {
>                V_MCFG_BANKALLOCATION_RBC |                     \
>                V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
>
> +
> +/* Hynix part of Overo (165MHz optimized) 6.06ns */
> +#define HYNIX_TDAL_165   6
> +#define HYNIX_TDPL_165   3
> +#define HYNIX_TRRD_165   2
> +#define HYNIX_TRCD_165   3
> +#define HYNIX_TRP_165    3
> +#define HYNIX_TRAS_165   7
> +#define HYNIX_TRC_165   10
> +#define HYNIX_TRFC_165  21
> +#define HYNIX_V_ACTIMA_165     \
> +               ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165,      \
> +                               HYNIX_TRAS_165, HYNIX_TRP_165,  \
> +                               HYNIX_TRCD_165, HYNIX_TRRD_165, \
> +                               HYNIX_TDPL_165, HYNIX_TDAL_165)
> +
> +#define HYNIX_TWTR_165   1
> +#define HYNIX_TCKE_165   1
> +#define HYNIX_TXP_165    2
> +#define HYNIX_XSR_165    24
> +#define HYNIX_V_ACTIMB_165     \
> +               ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165,     \
> +                               HYNIX_TXP_165, HYNIX_XSR_165)
> +
> +#define HYNIX_RASWIDTH_165     0x2
> +#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165)
> +
>  /* Hynix part of AM/DM37xEVM (200MHz optimized) */
>  #define HYNIX_TDAL_200         6
>  #define HYNIX_TDPL_200         3
> diff --git a/board/overo/config.mk b/board/overo/config.mk
> deleted file mode 100644
> index e7c471c..0000000
> --- a/board/overo/config.mk
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -#
> -# Overo uses OMAP3 (ARM-CortexA8) cpu
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -# Physical Address:
> -# 8000'0000 (bank0)
> -# A000/0000 (bank1)
> -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> -# (mem base + reserved)
> -
> -CONFIG_SYS_TEXT_BASE = 0x80008000
> diff --git a/board/overo/overo.c b/board/overo/overo.c
> index 3c60b06..dbe43ab 100644
> --- a/board/overo/overo.c
> +++ b/board/overo/overo.c
> @@ -31,6 +31,7 @@
>  #include <common.h>
>  #include <netdev.h>
>  #include <twl4030.h>
> +#include <linux/mtd/nand.h>
>  #include <asm/io.h>
>  #include <asm/arch/mmc_host_def.h>
>  #include <asm/arch/mux.h>
> @@ -126,6 +127,44 @@ int get_board_revision(void)
>        return revision;
>  }
>
> +#ifdef CONFIG_SPL_BUILD
> +/*
> + * Routine: get_board_mem_timings
> + * Description: If we use SPL then there is no x-loader nor config header
> + * so we have to setup the DDR timings ourself on both banks.
> + */
> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
> +               u32 *mr)
> +{
> +       *mr = MICRON_V_MR_165;
> +       switch (get_board_revision()) {

I think you will also need to update the get_board_revision function
to ensure that SPL works with very early Overo revisions.

Note this excerpt from the X-loader get_board_revision funtion:

	/* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
	/* these boards should return a revision number of 0                  */
	/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
#ifdef CONFIG_DRIVER_OMAP34XX_I2C
	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
	data = 0x01;
	i2c_write(0x4B, 0x29, 1, &data, 1);
	data = 0x0c;
	i2c_write(0x4B, 0x2b, 1, &data, 1);
	i2c_read(0x4B, 0x2a, 1, &data, 1);
#endif

Yup, ugly, but this is the only way to detect revision properly on those boards.

Regards,

Steve