[U-Boot] [PATCH] ftintc010.h: add header of ftintc010 interrupt controller

[Macpaul Lin]

add header definition of faraday interrupt controller

Signed-off-by: Macpaul Lin <macpaul at andestech.com>
---
 include/faraday/ftintc010.h |  101 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 101 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftintc010.h

diff --git a/include/faraday/ftintc010.h b/include/faraday/ftintc010.h
new file mode 100644
index 0000000..f2e004b
--- /dev/null
+++ b/include/faraday/ftintc010.h
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2012 Andes Technology Corp
+ * Macpaul Lin <macpaul at andestech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTINTC010 - Faraday Interrupt Controller
+ */
+#ifndef __FTINTC010_H
+#define __FTINTC010_H
+
+#ifndef __ASSEMBLY__
+
+struct ftintc010 {
+	unsigned int	irqsrc;		/* 0x00 - IRQ Source */
+	unsigned int	irqen;		/* 0x04 - IRQ Enable */
+	unsigned int	irqclr;		/* 0x08 - IRQ Interrupt Clear */
+	unsigned int	irqtrigmode;	/* 0x0C - IRQ Trigger Mode */
+	unsigned int	irqtriglevel;	/* 0x10 - IRQ Trigger Level */
+	unsigned int	status;		/* 0x14 - IRQ Status */
+	unsigned int	rsvd0[2];	/* 0x18-0x1C */
+	unsigned int	fiqsrc;		/* 0x20 - FIQ Source */
+	unsigned int	fiqen;		/* 0x24 - FIQ Enable */
+	unsigned int	fiqclr;		/* 0x28 - FIQ Interrupt Clear */
+	unsigned int	fiqtrigmode;	/* 0x2C - FIQ Trigger Mode */
+	unsigned int	fiqtriglevel;	/* 0x30 - FIQ Trigger Level */
+	unsigned int	fiqstatus;	/* 0x34 - FIQ Status */
+	unsigned int	rsvd1[6];	/* 0x38-0x4C */
+	unsigned int	rev;		/* 0x50 - Revision */
+
+	/* The following are Feature Registers */
+	unsigned int	frin;		/* 0x54 - Input Number */
+	unsigned int	frirqdl;	/* 0x58 - IRQ De-bounce Location */
+	unsigned int	frfiqdl;	/* 0x5C - FIQ De-bounce Location */
+};
+#endif /* __ASSEMBLY__ */
+
+/* 0x00 - IRQ Source Register */
+#define FTINTC010_IRQ_SRC(x)		(1 << x)
+
+/* 0x04 - IRQ Enable Register */
+#define FTINTC010_IRQ_EN(x)		(1 << x)
+
+/* 0x08 - IRQ Interrupt Clear Register */
+#define FTINTC010_IRQ_CLR(x)		(1 << x)
+
+/* 0x0C - IRQ Trigger Mode Register */
+#define FTINTC010_IRQ_TRIGMODE(x)	(1 << x)
+
+/* 0x10 - IRQ Trigger Level Register */
+#define FTINTC010_IRQ_TRIGLEVEL(x)	(1 << x)
+
+/* 0x14 - IRQ Status Register */
+#define FTINTC010_IRQ_ST(x)		(1 << x)
+
+/* 0x20 - FIQ Source Register */
+#define FTINTC010_FIQ_SRC(x)		(1 << x)
+
+/* 0x24 - FIQ Enable Register */
+#define FTINTC010_FIQ_EN(x)		(1 << x)
+
+/* 0x28 - FIQ Interrupt Clear Register */
+#define FTINTC010_FIQ_CLR(x)		(1 << x)
+
+/* 0x2C - FIQ Trigger Mode Register */
+#define FTINTC010_FIQ_TRIGMODE(x)	(1 << x)
+
+/* 0x30 - FIQ Trigger Level Register */
+#define FTINTC010_FIQ_TRIGLEVEL(x)	(1 << x)
+
+/* 0x34 - FIQ Status Register */
+#define FTINTC010_FIQ_ST(x)		(1 << x)
+
+/* 0x50 - Revision Register */
+#define FTINTC010_REV(x)		(((x) > 0) & 0xFFFFFF)
+
+/* 0x54 - Feature Register for Input Number */
+#define FTINTC010_FRIN_IRQNO(x)		(((x) > 8) & 0xFF)
+#define FTINTC010_FRIN_FIQNO(x)		(((x) > 0) & 0xFF)
+
+/* 0x58 - Feature Register for IRQ De-bounce Location */
+#define FTINTC010_IRQDL(x)		(1 << x)
+
+/* 0x5C - Feature Register for FIQ De-bounce Location */
+#define FTINTC010_FIQDL(x)		(1 << x)
+
+#endif	/* __FTINTC010_H */
-- 
1.7.3.5