[U-Boot] [PATCH 2/2] Exynos: Fix ARM Clock frequency calculation

[Chander Kashyap]

Dear Wolfgang Denk,

On 19 December 2011 14:29, Wolfgang Denk <wd at denx.de> wrote:

> Dear Chander Kashyap,
>
> In message <
> CANuQgHHq_+aZ6z100agOuaumeUyXwH-HL6aNPgrtOWBadEQaHQ at mail.gmail.com> you
> wrote:
> >
> > > In message <
> 1324275424-29468-3-git-send-email-chander.kashyap at linaro.org>
> > > you wrote:
> > > > Earliar ARM clock frequency was calculated by:
> > > > MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
> > > > It is fixed by calcuating it as follows:
> > >
> > > Um.... Comment and code disagree:
> > >
> > > > ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
> > >
> > > ...or is this just missing a paren?
> > >
> > > > +     dout_apll = get_pll_clk(APLL) / (core_ratio + 1);
> > > > +     dout_apll /= (core2_ratio + 1);
> > >
> > > This gives
> > >
> > >  ARMCLK=MOUTCORE/(DIVCORE + 1)/ (DIVCORE2 + 1)
> > >
> > > Please check if this is correct.
> > >
> >
> > Below is the scenario of selection.
> >                                       ____________
> > MOUTAPLL  --------------->| MUX_CORE |------------>MOUTCORE
> > MOUTMPLL --------------->|____________|
> >
> > Here MOUTAPLL is selected as input. So Parent is correct.
>
> You miss the point.
>
> Your comment:
>
>        ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
>
> is missing one opening brace.  Depending on where you insert it, the
> code may or may not match.
>
Thanks, I got it. Resend it again.

>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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>



-- 
with warm regards,
Chander Kashyap