[U-Boot] [PATCH] tegra: mmc: Support operation with dcache enabled

[Stephen Warren]

Simon Glass wrote at Wednesday, December 21, 2011 1:03 PM:
> When the data cache is enabled we must flush on write and invalidate
> on read. We also check that buffers are aligned to data cache lines
> boundaries. With recent work in U-Boot this should generally be the case
> but the warnings will catch problems.
> 
> Signed-off-by: Simon Glass <sjg at chromium.org>

Conceptually this seems fine, but shouldn't the MMC driver core be doing
the cache management, so all platforms without cache coherency can
benefit from it?

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nvpublic