[U-Boot] [PATCH] atmel nand patch CE don't care NAND

[Reinhard Meyer]

Dear Scott Wood, Michael Trimarchi,
>>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>>> index ab8bbb3..bda117a 100644
>>> --- a/drivers/mtd/nand/atmel_nand.c
>>> +++ b/drivers/mtd/nand/atmel_nand.c
>>> @@ -249,8 +249,13 @@ static void at91_nand_hwcontrol(struct mtd_info *mtd,
>>>   		if (ctrl&  NAND_ALE)
>>>   			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
>>>
>>> +		/*
>>> +		 * Nand CS don't care doesn't need the enable pin
>>> +		 */
>>> +#ifdef CONFIG_SYS_NAND_ENABLE_PIN
>>>   		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
>>>   				    !(ctrl&  NAND_NCE));
>>> +#endif
>>
>> New CONFIG symbols need to be documented, and this particular one should
>> probably be less generic.
>
> Sorry, ignore that -- I see it's not new (it should still be documented,
> but that's not this patch's problem).
>
> The code change itself looks OK, just needs a better commit
> message/comment. Some googling indicates that "CE don't care" refers to the
> ability to deassert the chip enable line once an operation has been
> initiated.  This seems to be different from not having control of CE at all
> (is it just always asserted on these boards?).

I agree that the code looks OK. Apparently it means that CE must be always asserted
(wired to GND) and that access to the chip is solely controlled by RE and WE.
According to (for example) the Samsung K9F2G08X0B data sheet this is possible.

I also agree that the message/comment should point this out for future understanding.

Best Regards,
Reinhard