[U-Boot] [PATCH 12/15] ATMEL: fix dataflash (dirty)
Andreas Bießmann
andreas.devel at googlemail.com
Fri Feb 18 13:33:38 CET 2011
Am 18.02.2011 13:50, schrieb Reinhard Meyer:
> Signed-off-by: Reinhard Meyer <u-boot at emk-elektronik.de>
> ---
> drivers/spi/atmel_dataflash_spi.c | 94 ++++++++++++++++++++++--------------
> include/dataflash.h | 1 -
> 2 files changed, 57 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c
> index 4a5c4aa..6e632cc 100644
> --- a/drivers/spi/atmel_dataflash_spi.c
> +++ b/drivers/spi/atmel_dataflash_spi.c
> @@ -21,13 +21,21 @@
>
> #include <common.h>
> #ifndef CONFIG_AT91_LEGACY
> -#define CONFIG_AT91_LEGACY
> -#warning Please update to use C structur SoC access !
> +# define CONFIG_AT91_LEGACY
this would be CONFIG_ATMEL_LEGACY
> +# warning Please update to use C structur SoC access !
> #endif
> -#include <asm/arch/hardware.h>
> +#include <common.h>
> +#include <spi.h>
> +#include <malloc.h>
> +
> +#include <asm/io.h>
> +
> #include <asm/arch/clk.h>
> +#include <asm/arch/hardware.h>
> +
> +#include "atmel_spi.h"
> +
> #include <asm/arch/gpio.h>
> -#include <asm/arch/io.h>
> #include <asm/arch/at91_pio.h>
> #include <asm/arch/at91_spi.h>
>
> @@ -41,18 +49,18 @@
> void AT91F_SpiInit(void)
> {
> /* Reset the SPI */
> - writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
> + writel(AT91_SPI_SWRST, ATMEL_BASE_SPI0 + AT91_SPI_CR);
>
> /* Configure SPI in Master Mode with No CS selected !!! */
> writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
> - AT91_BASE_SPI + AT91_SPI_MR);
> + ATMEL_BASE_SPI0 + AT91_SPI_MR);
>
> /* Configure CS0 */
> writel(AT91_SPI_NCPHA |
> (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
> (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
> ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
> - AT91_BASE_SPI + AT91_SPI_CSR(0));
> + ATMEL_BASE_SPI0 + AT91_SPI_CSR(0));
>
> #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
> /* Configure CS1 */
> @@ -60,7 +68,7 @@ void AT91F_SpiInit(void)
> (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
> (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
> ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
> - AT91_BASE_SPI + AT91_SPI_CSR(1));
> + ATMEL_BASE_SPI0 + AT91_SPI_CSR(1));
> #endif
> #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS2
> /* Configure CS2 */
> @@ -68,7 +76,7 @@ void AT91F_SpiInit(void)
> (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
> (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
> ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
> - AT91_BASE_SPI + AT91_SPI_CSR(2));
> + ATMEL_BASE_SPI0 + AT91_SPI_CSR(2));
> #endif
> #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
> /* Configure CS3 */
> @@ -76,21 +84,22 @@ void AT91F_SpiInit(void)
> (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
> (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
> ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
> - AT91_BASE_SPI + AT91_SPI_CSR(3));
> + ATMEL_BASE_SPI0 + AT91_SPI_CSR(3));
> #endif
>
> /* SPI_Enable */
> - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
> + writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
>
> - while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
> + while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_SPIENS))
> + ;
>
> /*
> * Add tempo to get SPI in a safe state.
> * Should not be needed for new silicon (Rev B)
> */
> udelay(500000);
> - readl(AT91_BASE_SPI + AT91_SPI_SR);
> - readl(AT91_BASE_SPI + AT91_SPI_RDR);
> + readl(ATMEL_BASE_SPI0 + AT91_SPI_SR);
> + readl(ATMEL_BASE_SPI0 + AT91_SPI_RDR);
>
> }
>
> @@ -100,33 +109,33 @@ void AT91F_SpiEnable(int cs)
>
> switch (cs) {
> case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
> - mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
> + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
> mode &= 0xFFF0FFFF;
> writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
> - AT91_BASE_SPI + AT91_SPI_MR);
> + ATMEL_BASE_SPI0 + AT91_SPI_MR);
> break;
> case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
> - mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
> + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
> mode &= 0xFFF0FFFF;
> writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
> - AT91_BASE_SPI + AT91_SPI_MR);
> + ATMEL_BASE_SPI0 + AT91_SPI_MR);
> break;
> case 2: /* Configure SPI CS2 for Serial DataFlash AT45DBxx */
> - mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
> + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
> mode &= 0xFFF0FFFF;
> writel(mode | ((AT91_SPI_PCS2_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
> - AT91_BASE_SPI + AT91_SPI_MR);
> + ATMEL_BASE_SPI0 + AT91_SPI_MR);
> break;
> case 3:
> - mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
> + mode = readl(ATMEL_BASE_SPI0 + AT91_SPI_MR);
> mode &= 0xFFF0FFFF;
> writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
> - AT91_BASE_SPI + AT91_SPI_MR);
> + ATMEL_BASE_SPI0 + AT91_SPI_MR);
> break;
> }
>
> /* SPI_Enable */
> - writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
> + writel(AT91_SPI_SPIEN, ATMEL_BASE_SPI0 + AT91_SPI_CR);
> }
>
> unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
> @@ -134,37 +143,48 @@ unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
> unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
> {
> unsigned int timeout;
> + unsigned int timebase;
>
> pDesc->state = BUSY;
>
> - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
> + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
> + ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
>
> /* Initialize the Transmit and Receive Pointer */
> - writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
> - writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
> + writel((unsigned int)pDesc->rx_cmd_pt,
> + ATMEL_BASE_SPI0 + AT91_SPI_RPR);
> + writel((unsigned int)pDesc->tx_cmd_pt,
> + ATMEL_BASE_SPI0 + AT91_SPI_TPR);
>
> /* Intialize the Transmit and Receive Counters */
> - writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
> - writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
> + writel(pDesc->rx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_RCR);
> + writel(pDesc->tx_cmd_size, ATMEL_BASE_SPI0 + AT91_SPI_TCR);
>
> if (pDesc->tx_data_size != 0) {
> /* Initialize the Next Transmit and Next Receive Pointer */
> - writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
> - writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
> + writel((unsigned int)pDesc->rx_data_pt,
> + ATMEL_BASE_SPI0 + AT91_SPI_RNPR);
> + writel((unsigned int)pDesc->tx_data_pt,
> + ATMEL_BASE_SPI0 + AT91_SPI_TNPR);
>
> /* Intialize the Next Transmit and Next Receive Counters */
> - writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
> - writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
> + writel(pDesc->rx_data_size,
> + ATMEL_BASE_SPI0 + AT91_SPI_RNCR);
> + writel(pDesc->tx_data_size,
> + ATMEL_BASE_SPI0 + AT91_SPI_TNCR);
> }
>
> /* arm simple, non interrupt dependent timer */
> - reset_timer_masked();
> + timebase = get_timer(0);
> timeout = 0;
>
> - writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
> - while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
> - ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
> - writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
> + writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN,
> + ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
> + while (!(readl(ATMEL_BASE_SPI0 + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
> + ((timeout = get_timer(timebase)) < CONFIG_SYS_SPI_WRITE_TOUT))
> + ;
> + writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
> + ATMEL_BASE_SPI0 + AT91_SPI_PTCR);
> pDesc->state = IDLE;
>
> if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
> diff --git a/include/dataflash.h b/include/dataflash.h
> index 63b3bf9..96ac097 100644
> --- a/include/dataflash.h
> +++ b/include/dataflash.h
> @@ -34,7 +34,6 @@
> #define _DataFlash_h
>
>
> -#include <asm/arch/hardware.h>
> #include "config.h"
>
> /*number of protected area*/
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