[U-Boot] [PATCH 2/2] MX53: Add initial support for MX53ARD board
Jason Liu
liu.h.jason at gmail.com
Mon May 16 07:40:13 CEST 2011
Hi, Fabio,
[...]
> +static void setup_iomux_uart(void)
> +{
> + /* UART1 RXD */
> + mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
> + PAD_CTL_ODE_OPENDRAIN_ENABLE);
> + mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
> +
> + /* UART1 TXD */
> + mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
> + mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
> + PAD_CTL_ODE_OPENDRAIN_ENABLE);
> +}
> +
> +#ifdef CONFIG_FSL_ESDHC
> +struct fsl_esdhc_cfg esdhc_cfg[1] = {
> + {MMC_SDHC1_BASE_ADDR, 1},
> +};
Why only support one mmc slot?
> +
> +int board_mmc_getcd(u8 *cd, struct mmc *mmc)
> +{
> + *cd = mxc_gpio_get(1); /*GPIO1*/
> +
> + return 0;
> +}
Dito, here /*GPIO1*/ should be /*GPIO0_1*/ ?
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + u32 index;
> + s32 status = 0;
> +
> + for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
> + switch (index) {
> + case 0:
> + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA0,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA1,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA2,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_SD1_DATA3,
> + IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX53_PIN_EIM_DA13,
> + IOMUX_CONFIG_ALT1);
> +
> + mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
> + PAD_CTL_DRV_HIGH);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
> + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
> + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
> + break;
> +
> + default:
> + printf("Warning: you configured more ESDHC controller"
> + "(%d) as supported by the board(1)\n",
> + CONFIG_SYS_FSL_ESDHC_NUM);
> + return status;
Here is wrong, the board can support up to 2 esdhc controller.
> + }
> + status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
> + }
> +
> + return status;
> +}
> +#endif
> +
[..]
> +void weim_cs1_settings()
> +{
> + unsigned int reg;
> +
> + writel(0x20001, (WEIM_BASE_ADDR + 0x18));
> + writel(0x0, (WEIM_BASE_ADDR + 0x1C));
> + writel(0x16000202, (WEIM_BASE_ADDR + 0x20));
> + writel(0x00000002, (WEIM_BASE_ADDR + 0x24));
> + writel(0x16002082, (WEIM_BASE_ADDR + 0x28));
> + writel(0x00000000, (WEIM_BASE_ADDR + 0x2C));
> + writel(0x00000000, (WEIM_BASE_ADDR + 0x90));
Can we use struct access here?
> +
> + /* specify 64 MB on CS1 and CS0 */
> + reg = readl(IOMUXC_BASE_ADDR + 0x4);
> + reg &= ~0x3F;
> + reg |= 0x1B;
> + writel(reg, (IOMUXC_BASE_ADDR + 0x4));
> +}
No need () for OMUXC_BASE_ADDR + 0x4 here ?
> +
> +int board_early_init_f(void)
> +{
> + setup_iomux_uart();
> + return 0;
> +}
> +
> +int board_init(void)
> +{
> + gd->bd->bi_arch_number = MACH_TYPE_MX53_SMD;
Wrong!, This is ARD board support, not SMD, right?
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +
> + weim_smc911x_iomux();
> + weim_cs1_settings();
> +
> +#ifdef CONFIG_SMC911X
> + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + return rc;
> +}
> +
> +int checkboard(void)
> +{
> + puts("Board: MX53ARD\n");
> +
> + return 0;
> +}
[...]
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CONFIG_SYS_MEMTEST_START 0x70000000
> +#define CONFIG_SYS_MEMTEST_END 0x10000
Wrong!, the end address should not smaller than start!
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_HZ 1000
> +#define CONFIG_CMDLINE_EDITING
> +
> +/* Stack sizes */
> +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
> +
> +/* Physical Memory Map */
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define PHYS_SDRAM_1 CSD0_BASE_ADDR
> +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
Wrong!!, does ARD only have 512M memory? ARD should have 1G memroy.
> +
> +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
> +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
> +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
> +#define CONFIG_ENV_SIZE (8 * 1024)
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_SYS_BOOTMAPSZ 0x800000
> +
> +#endif /* __CONFIG_H */
> --
> 1.6.0.4
>
>
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