[U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1

[David Jander]

i.MX51 PLL1 seems to have stability problems. It is advised to not use it,
although it is unclear whether all boards and/or chip revisions have this
problem. Using PLL2 for the core and DDR2 seems to fix the problem.
No official errata yet.

Signed-off-by: David Jander <david at protonic.nl>
---
 arch/arm/cpu/armv7/mx5/lowlevel_init.S |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 96ebfe2..e1d6c35 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -153,7 +153,11 @@
 	mov r1, #0x4
 	str r1, [r0, #CLKCTL_CCSR]
 
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	setup_pll PLL1_BASE_ADDR, 216
+#else
 	setup_pll PLL1_BASE_ADDR, 800
+#endif
 
 #if defined(CONFIG_MX51)
 	setup_pll PLL3_BASE_ADDR, 665
@@ -165,7 +169,11 @@
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	setup_pll PLL2_BASE_ADDR, 800
+#else
 	setup_pll PLL2_BASE_ADDR, 665
+#endif
 
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
@@ -197,7 +205,11 @@
 #endif
 	str r1, [r0, #CLKCTL_CACRR]
 	/* Switch ARM back to PLL 1 */
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	mov r1, #0x00000104 /* Set ARM/DDR to PLL2 */
+#else
 	mov r1, #0
+#endif
 	str r1, [r0, #CLKCTL_CCSR]
 
 #if defined(CONFIG_MX51)
@@ -228,7 +240,11 @@
 	/* Use PLL 2 for UART's, get 66.5MHz from it */
 	ldr r1, =0xA5A2A020
 	str r1, [r0, #CLKCTL_CSCMR1]
+#if defined(CONFIG_MX51_AVOID_PLL1)
+	ldr r1, =0x0104041a /* Adjust dividers for 800MHz on PLL2 */
+#else
 	ldr r1, =0x00C30321
+#endif
 	str r1, [r0, #CLKCTL_CSCDR1]
 #elif defined(CONFIG_MX53)
 	ldr r1, [r0, #CLKCTL_CSCDR1]
-- 
1.7.4.1