[U-Boot] [PATCH v4 07/14] OMAP3: Add optimal SDRC autorefresh control values

[Tom Rini]

This adds the optimal SDRC autorefresh control register values for
100Mhz, 133MHz, 165MHz and 200MHz clocks.  We switch to using this
to provide the default 165MHz value.

Signed-off-by: Tom Rini <trini at ti.com>
---
 arch/arm/include/asm/arch-omap3/mem.h |   16 +++++++++++-----
 1 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 12ff3b0..912c737 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -49,6 +49,16 @@ enum {
 #define SDRC_SHARING	0x00000100
 #define SDRC_MR_0_SDR	0x00000031
 
+/*
+ * SDRC autorefresh control values.  This register consists of autorefresh
+ * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
+ * counter is a result of ( tREFI / tCK ) - 50.
+ */
+#define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
+#define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
+
 #define DLL_OFFSET		0
 #define DLL_WRITEDDRCLKX2DIS	1
 #define DLL_ENADLL		1
@@ -168,10 +178,6 @@ enum {
 #define MICRON_RASWIDTH		0x2
 #define MICRON_V_MCFG(size)	MCFG((size), MICRON_RASWIDTH)
 
-#define MICRON_ARCV				2030
-#define MICRON_ARE				0x1
-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
-
 #define MICRON_BL				0x2
 #define MICRON_SIL				0x0
 #define MICRON_CASL				0x3
@@ -214,7 +220,7 @@ enum {
 #define V_ACTIMA_165		MICRON_V_ACTIMA_165
 #define V_ACTIMB_165		MICRON_V_ACTIMB_165
 #define V_MCFG			MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
-#define V_RFR_CTRL		MICRON_V_RFR_CTRL
+#define V_RFR_CTRL		SDP_3430_SDRC_RFR_CTRL_165MHz
 #define V_MR			MICRON_V_MR
 #endif
 
-- 
1.7.0.4