[U-Boot] [PATCH 07/11] MIPS: extend cache initialization for MIPS24K and MIPS34K cores

Marek Vasut marek.vasut at gmail.com
Fri Nov 25 09:46:07 CET 2011


> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck at googlemail.com>
> ---
>  arch/mips/cpu/mips32/cache.S     |   18 ++++++++++++++++++
>  arch/mips/include/asm/mipsregs.h |    9 ++++++++-
>  2 files changed, 26 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
> index e683e8b..4801511 100644
> --- a/arch/mips/cpu/mips32/cache.S
> +++ b/arch/mips/cpu/mips32/cache.S
> @@ -34,6 +34,14 @@
>  #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
>  #endif
> 
> +#ifdef CONFIG_SYS_CPU_MIPS24K

#if defined(...) || defined(...) maybe?

> +#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
> +#endif
> +
> +#ifdef CONFIG_SYS_CPU_MIPS34K
> +#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
> +#endif
> +
>  #define RA		t8
> 
>  /*
> @@ -81,7 +89,12 @@
>   */
>  LEAF(mips_init_icache)
>  	blez		a1, 9f
> +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
> +	mtc0		zero, CP0_ITAGLO
> +	mtc0		zero, CP0_IDATALO
> +#else
>  	mtc0		zero, CP0_TAGLO
> +#endif
>  	/* clear tag to invalidate */
>  	PTR_LI		t0, INDEX_BASE
>  	PTR_ADDU	t1, t0, a1
> @@ -106,7 +119,12 @@ LEAF(mips_init_icache)
>   */
>  LEAF(mips_init_dcache)
>  	blez		a1, 9f
> +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
> +	mtc0		zero, CP0_DTAGLO
> +	mtc0		zero, CP0_DDATALO
> +#else
>  	mtc0		zero, CP0_TAGLO
> +#endif
>  	/* clear all tags */
>  	PTR_LI		t0, INDEX_BASE
>  	PTR_ADDU	t1, t0, a1
> diff --git a/arch/mips/include/asm/mipsregs.h
> b/arch/mips/include/asm/mipsregs.h index 15a9fd5..07a3cf6 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -93,7 +93,14 @@
>   * These registers are listed for completeness and are intended
>   * for usage in assembly code.
>   */
> -#define CP0_EBASE $15,1
> +#define CP0_EBASE	$15,1
> +/* L1 I-Cache */
> +#define CP0_ITAGLO	$28
> +#define CP0_IDATALO	$28,1
> +#define CP0_IDATAHI	$29,1
> +/* L1 D-Cache */
> +#define CP0_DTAGLO	$28,2
> +#define CP0_DDATALO	$28,3
> 
>  /*
>   * Coprocessor 0 Set 1 register names

Otherwise, this looks good:

Acked-by: Marek Vasut <marek.vasut at gmail.com>


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