[U-Boot] [PATCH v2 07/10] MIPS: extend cache initialization for recent MIPS CPU cores

[Daniel Schwierzeck]

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck at googlemail.com>
---
Changes for v2:
 - updated patch subject
 - removed CPU specific #ifdefs
 - added description for config option CONFIG_SYS_MIPS_CACHE_EXT_INIT
   to README

 README                           |    5 +++++
 arch/mips/cpu/mips32/cache.S     |   10 ++++++++++
 arch/mips/include/asm/mipsregs.h |    9 ++++++++-
 3 files changed, 23 insertions(+), 1 deletions(-)

diff --git a/README b/README
index 07f1d11..834dd45 100644
--- a/README
+++ b/README
@@ -409,6 +409,11 @@ The following options need to be configured:
 			CONF_CM_CACHABLE_CUW
 			CONF_CM_CACHABLE_ACCELERATED
 
+		CONFIG_SYS_MIPS_CACHE_EXT_INIT
+
+		Enable this to use extended cache initialization for recent
+		MIPS CPU cores.
+
 		CONFIG_SYS_XWAY_EBU_BOOTCFG
 
 		Special option for Lantiq XWAY SoCs for booting from NOR flash.
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8b..316e961 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -81,7 +81,12 @@
  */
 LEAF(mips_init_icache)
 	blez		a1, 9f
+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
+	mtc0		zero, CP0_ITAGLO
+	mtc0		zero, CP0_IDATALO
+#else
 	mtc0		zero, CP0_TAGLO
+#endif
 	/* clear tag to invalidate */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1
@@ -106,7 +111,12 @@ LEAF(mips_init_icache)
  */
 LEAF(mips_init_dcache)
 	blez		a1, 9f
+#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
+	mtc0		zero, CP0_DTAGLO
+	mtc0		zero, CP0_DDATALO
+#else
 	mtc0		zero, CP0_TAGLO
+#endif
 	/* clear all tags */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 15a9fd5..07a3cf6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -93,7 +93,14 @@
  * These registers are listed for completeness and are intended
  * for usage in assembly code.
  */
-#define CP0_EBASE $15,1
+#define CP0_EBASE	$15,1
+/* L1 I-Cache */
+#define CP0_ITAGLO	$28
+#define CP0_IDATALO	$28,1
+#define CP0_IDATAHI	$29,1
+/* L1 D-Cache */
+#define CP0_DTAGLO	$28,2
+#define CP0_DDATALO	$28,3
 
 /*
  * Coprocessor 0 Set 1 register names
-- 
1.7.7.2