[U-Boot] MPC8536 problems II

[David Lynch Jr.]

Trying again, with an effort to be more concise. 

What are the minimums that need to be setup correctly to access DDR for
an MPC8536 in u-boot ? This is probably my most important question. 
I do not want to fixate on DDR controler timing issues, when the Local
Access Windows, TLB's or L2 Cache are also likely culprits.  

Do the TLB's have to be correct ? Are the default u-boot TLB's likely to
work for DDR starting at 0 ?

I believe the MPC8536 u-boot configuration uses the L2 as memory during
early startup. Does anything cache related have to be changed when DDR
is enabled ?

I am not seeing where the Local Access Windows are set for DDR, they are
set for NAND, NOR, ... most everything else. Do they need to be set for
DDR ?

I grasp that getting reliable operation requires perfect programming of
the DDR controller, but right now unreliable would be a step forward. 
What are the most likely DDR register culprits for complete inability to
read. 

I can write DDR - meaning the operation completes. I have no idea
whether any data is actually written, but any attempt to read leaves the
processor waiting forever at the instruction reading memory. 
 
I am trying per Wolfgang's recommendations to switch to the u-boot git
tree rather than 2009.03. But that does not appear to build. 




On Wed, 2011-11-23 at 23:44 -0500, David Lynch Jr. wrote:
> I am bringing u-boot-2009.03-rc1 up on an MPC8536 target, and I am
> having some problems reading DDR, suggestions would be greatly
> appreciated. 
> I am using this particular u-boot, because the client succeeded in
> getting that working on an MPC8536DS (that I do not have access to). I
> can not even get the serial port working on the target with newer
> versions of u-boot. 
> This target is much simpler than the MPC8526DS and I have disabled
> everything but Serial, DDR, and NOR in the board configuration file. The
> only thing that must work is booting linux. This board has no PIXIS, no
> ISC307, and the DDR does not have SPD.  
> I now appear to have everything but DDR working. I can not get u-boot to
> relocate to ram. Writing to RAM seems to work - in the sense there are
> no faults and writes do not hang, but reading RAM stalls the instruction
> forever without error. 
> I am using a BDI3000 - which I am not fluent in. The BDI3000
> configuration is minimal - only enough to read/write/erase NOR, and
> manipulate the processor. The BDI3000 faults when reading DDR - but it
> is not setup for that. 
> The MPC8536DS code to setup DDR without SPD would not compile as it was,
> but I beleive I have fixed that. I have played with myriads of DDR
> controller register value changes without change in behavior. As this is
> a total read failure - rather than just unreliable operation I am
> leaning towards looking for other culprits - though the DDR
> configuration is still high on the list as u-boot works ont he
> development system and the remaining difference of consequence is that
> the DDR is manually programmed on the target. 
> Access to the hardware is severely limited - it is two hours away in a
> secure facility, and I must try as much as possible during the limited
> time I have access. 
> 
> 
> 
> 
>