[U-Boot] [PATCH v2 4/7] mmc: dcache: allocate cache aligned buffer for scr and switch_status

[Anton Staaf]

Currently the sd_change_freq function allocates two buffers on the
stack that it passes down to the MMC device driver.  These buffers
could be unaligned to the L1 dcache line size.  This causes problems
when using DMA and with caches enabled.

This patch correctly cache alignes the buffers used for reading the
scr register and switch status values from an MMC device.

Signed-off-by: Anton Staaf <robotboy at chromium.org>
Acked-by: Mike Frysinger <vapier at gentoo.org>
Cc: Lukasz Majewski <l.majewski at samsung.com>
Cc: Mike Frysinger <vapier at gentoo.org>
Cc: Albert ARIBAUD <albert.u.boot at aribaud.net>
---
 drivers/mmc/mmc.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 391bc2b..ba6fbfe 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -702,8 +702,8 @@ int sd_change_freq(struct mmc *mmc)
 {
 	int err;
 	struct mmc_cmd cmd;
-	uint scr[2];
-	uint switch_status[16];
+	ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
+	ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
 	struct mmc_data data;
 	int timeout;
 
@@ -731,7 +731,7 @@ int sd_change_freq(struct mmc *mmc)
 	timeout = 3;
 
 retry_scr:
-	data.dest = (char *)&scr;
+	data.dest = (char *)scr;
 	data.blocksize = 8;
 	data.blocks = 1;
 	data.flags = MMC_DATA_READ;
@@ -773,7 +773,7 @@ retry_scr:
 	timeout = 4;
 	while (timeout--) {
 		err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
-				(u8 *)&switch_status);
+				(u8 *)switch_status);
 
 		if (err)
 			return err;
@@ -787,7 +787,7 @@ retry_scr:
 	if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
 		return 0;
 
-	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)&switch_status);
+	err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
 
 	if (err)
 		return err;
-- 
1.7.3.1