[U-Boot] [PATCH 4/6] davinci_emac: fix for running with dcache enabled

[Anton Staaf]

On Mon, Oct 10, 2011 at 10:44 AM, Wolfgang Denk <wd at denx.de> wrote:
> Dear Mike Frysinger,
>
> In message <201110101124.22548.vapier at gentoo.org> you wrote:
>>
>> > See the rest of the thread.  I had applied this patch set to a loal
>> > tree, but it was breaking hundreds of systems, so had to back out the
>> > patches again.
>> >
>> > I'm eager to get this code in myself, but it needs to be compile-clean
>> > at least and harmless to all boards that don't actually reference that
>> > code.
>>
>> sorry, but the rest of what thread ?  i missed that there were issues and was
>> wondering why they weren't in the published master branch yet ...
>
> There are actually three parts to this storey:
>
> Thisi s the original patch series, which I applied to a local test
> branch with the intention to pull into mainline:
>
> 10/04 Anton Staaf        [U-Boot] [PATCH v2 0/7] Add cache line alignment support
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111026
>
> Then I noticed that this broke all PPC4xx boards, and asked Stefan to
> fix this problem.  Stefan did:
>
> 10/07 Stefan Roese       [PATCH 1/2] ppc: Include <asm/cache.h> in common.h
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111482
>
> When PPC was building again, I tested it on ARM (which I assumed was
> OK, given that this was Anton's primary architecture).  That was when
> I finally gave up, see

Yes, the patches expose the fact that almost no boards define
CONFIG_SYS_CACHELINE_SIZE.
I am working on a "solution" for this.  My first thought is to add defines for
CONFIG_SYS_CACHELINE_SIZE in all of the arch cache.h files that
currently do not have them.
This would be all cache.h files other than the PPC one.  But this
could be a huge amount of work
to look up all of the arch cacheline sizes.  So I am thinking of
putting in a wrong, but large power
of two so that boards will build and probably work.  But will
certainly need to be fixed up...

Another solution would be to do the above and define
CONFIG_SYS_CACHELINE_SIZE as a
large (128?) value and then indicate that that config is to deprecated
in favor of Mikes suggestion
of using the Linux CACHE BITS defines.  Then we can move boards over
to that mechanism
over time, and in the mean time all boards will compile, and
architectures/boards that correctly
define their cacheline size will function correctly, and
architectures/boards that use the large default
will most likely function correctly...

-Anton

> 10/09 To:Anton Staaf     Re: [U-Boot] [PATCH v2 0/7] Add cache line alignment support
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111713
>
>
> Best regards,
>
> Wolfgang Denk
>
> --
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