[U-Boot] U-boot mainline test report on BeagleBoard

Simon Glass sjg at chromium.org
Tue Sep 13 18:03:10 CEST 2011


Hi,

On Tue, Sep 13, 2011 at 8:57 AM, Tom Rini <tom.rini at gmail.com> wrote:
> On Mon, Sep 12, 2011 at 7:29 PM, Joel A Fernandes <agnel.joel at gmail.com> wrote:
>> [resending to list as it bounced]
>>
>> On Tue, Sep 6, 2011 at 10:24 PM, Fernandes, Joel A <joelagnel at ti.com> wrote:
>>> Hi,
>>>
>>> Here are some problems I see currently with the today's mainline U-boot not seen with v2011.06 Just sharing them here.
>>>
>>> HEAD: 05f64ae996a51e32ef47e0db2c806e704606606e: led: remove camel casing of led identifiers globally
>> ..
>>> **** SMSC USB device is not detected in scan
>>>
>>> OMAP3 beagleboard.org # usb start
>>> (Re)start USB...
>>> USB:   Register 1313 NbrPorts 3
>>> USB EHCI 1.00
>>> scanning bus for devices... EHCI timed out on TD - token=0x80008c80
>>> 2 USB Device(s) found
>>>       scanning bus for storage devices... 0 Storage Device(s) found
>>>       scanning bus for ethernet devices... 0 Ethernet Device(s) found
>>> OMAP3 beagleboard.org #
>>
>> [Joel Fernandes]
>>
>> Disabling the I, D and L2 cache makes us able to detect the ethernet device.
>>
>> In board config,
>> #define CONFIG_SYS_ICACHE_OFF
>> #define CONFIG_SYS_DCACHE_OFF
>> #define CONFIG_SYS_L2CACHE_OFF
>>
>> Just CC'ing Aneesh as well as I believe he authored these patches:
>>
>> Commits:
>> e05f007 arm: minor fixes for cache and mmu handling
>> c2dd0d4 armv7: integrate cache maintenance support
>> e47f2db armv7: rename cache related CONFIG flags
>> 2c451f7 armv7: cache maintenance operations for armv7
>
> So, something here is "up" and I'm not sure what.  On a dm365evm, when
> I tested it a few weeks back I also needed to disable the caches to
> get networking working.  But that's unacceptable as a real solution
> since it just kills performance (I thought U-Boot wasn't working the
> first time I tried, and then when Oh, Wow, this is Bad).

Doesn't Beagleboard rely on USB Ethernet? If so, which type of USB
does it use? I think the EHCI code has support for caches, but not
sure about the rest. Failure to submit an urb could just mean that it
wasn't flushed out the cache. If so, it should be fairly easy to fix
by following along with the EHCI code - you just need to flush the
buffer when writing and invalidate before reading.

Regarding disabling caches, this was the default behaviour before
Aneesh's patches, so you are no worse off :-)

Regards,
Simon

>
> --
> Tom
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