[U-Boot] [PATCH 1/5] da830: disable cache usage due to coherency issues

[Nick Thompson]

On 14/09/11 06:54, Netagunte, Nagabhushana wrote:
> Nick,
>
> I am seeing this issue on da830/da850/dm36x/dm644x.

Strange that I have seen no issue with da830 (OMAP-L137 v1.0 & v1.1 - don't have any v2.0 yet) when tftp'ing the kernel. I do get very occasional errors, but have put this down to network packet loss.

The v1.0 and v1.1 parts do have a d-cache errata, so we only get to use the d-cache in write through mode. This would mean that TCP packet data writes by the processor would never have a coherency problem. Reads could still have an issue, but I think the explanation provided so far referred to TCP packet sending...?

This vintage of da830 will always have to use write trough mode, so there should be no issue...?

> I agree that u-boot will be faster with cache enabled. And also, TI wants it to be enabled soon. Since so many patches are lined u, we don't up-streaming them to get hampered because of this issue. So, we are trying to push this 
> Patch. We are committed come up with appropriate patch to fix the EMAC and coherency issue. 
>
> Meanwhile, we are trying to gather info about earlier patch/changes which disabled cache so that community understands the known issue.

Boot time is critical to us. I can't ship without cache enabled. I can use my own _config.h of course to work around it I think, but I don't understand why you think there is an issue to fix on da830 yet. With a working d-cache I can imagine such a problem though.

> Also, one more engineer observed the issue with EMAC, I will send his mail to you. 
>
> Regards,
> Nag
> On Wed, Aug 31, 2011 at 15:09:35, Nick Thompson wrote:
>> On 31/08/11 06:40, Netagunte, Nagabhushana wrote:
>>> Mike,
>>>
>>> We will address cache coherency issues soon after these patches.
>>> Earlier also, chache was disabled. Only due to new cache management Framework which was added recently, it is explicitly needed to be indicated to turn off cache. 
>>>
>>> Since fixing the cache coherency issues with EMAC will take some time, I want this patch to go in mainline so that issue doesn't crop up for People who use u-boot.
>>>
>>> Regards,
>>> Nag
>>>
>> Which device(s) does this occur on? I have a lot of OMAP-L137 (EVM and custom) boards with cache enabled and no problems tftp'ing the kernel.
>>
>> On the other hand tftp and kernel CRC checking are much faster with cache enabled.
>>
>> Nick.
>>