[U-Boot] [PATCH 2/4] Armada100: Add SPI support for Marvell gplugD

[Ajay Bhargav]

This patch add SPI driver support for Marvell gplugD.

Signed-off-by: Ajay Bhargav <ajay.bhargav at einfochips.com>
---
 arch/arm/include/asm/arch-armada100/armada100.h |   19 +++++++++++++++++++
 arch/arm/include/asm/arch-armada100/mfp.h       |    6 ++++++
 board/Marvell/gplugd/gplugd.c                   |   12 ++++++++++++
 include/configs/gplugd.h                        |    5 +++++
 4 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
index c449d4e..a8181b6 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -45,6 +45,10 @@
 #define FE_CLK_RST		0x1
 #define FE_CLK_ENA		0x8
 
+/* SSP2 Clock Control */
+#define SSP2_APBCLK		0x01
+#define SSP2_FNCLK		0x02
+
 /* Register Base Addresses */
 #define ARMD1_DRAM_BASE		0xB0000000
 #define ARMD1_FEC_BASE		0xC0800000
@@ -175,5 +179,20 @@ struct armd1apb1_registers {
 	u32 ac97;	/*0x084*/
 };
 
+/*
+* APB2 Clock Reset/Control Registers
+* Refer Datasheet Appendix A.11
+*/
+struct armd1apb2_registers {
+	u32 pad1[0x01C - 0x000];
+	u32 ssp1_clkrst;		/* 0x01C */
+	u32 ssp2_clkrst;		/* 0x020 */
+	u32 pad2[0x04C - 0x020 - 4];
+	u32 ssp3_clkrst;		/* 0x04C */
+	u32 pad3[0x058 - 0x04C - 4];
+	u32 ssp4_clkrst;		/* 0x058 */
+	u32 ssp5_clkrst;		/* 0x05C */
+};
+
 #endif /* CONFIG_ARMADA100 */
 #endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
index da76b58..d48251a 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -83,6 +83,12 @@
 #define MFP101_ETH_MDIO		(MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
 #define MFP103_ETH_RXDV		(MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
 
+/* SPI */
+#define MFP107_SSP2_RXD		(MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+#define MFP108_SSP2_TXD		(MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+#define MFP110_SSP2_CS		(MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP111_SSP2_CLK		(MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
+
 /* More macros can be defined here... */
 
 #define MFP_PIN_MAX	117
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index b4f7f81..42c8389 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -72,6 +72,12 @@ int board_early_init_f(void)
 		MFP101_ETH_MDIO,
 		MFP103_ETH_RXDV,
 
+		/* SSP2 */
+		MFP107_SSP2_RXD,
+		MFP108_SSP2_TXD,
+		MFP110_SSP2_CS,
+		MFP111_SSP2_CLK,
+
 		MFP_EOC		/*End of configuration*/
 	};
 	/* configure MFP's */
@@ -81,6 +87,9 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct armd1apb2_registers *apb2_regs =
+		(struct armd1apb2_registers *)ARMD1_APBC2_BASE;
+
 	/* arch number of Board */
 	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
 	/* adress of boot parameters */
@@ -90,6 +99,9 @@ int board_init(void)
 	udelay(10);
 	/* Deassert PHY_RST# */
 	gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
+
+	/* Enable SSP2 clock */
+	writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
 	return 0;
 }
 
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 5f72163..527a0c8 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -91,6 +91,11 @@
 /* GPIO Configuration for PHY */
 #define CONFIG_SYS_GPIO_PHY_RST		104	/* GPIO104 */
 
+/* SPI Support */
+#define CONFIG_ARMADA100_SPI
+#define CONFIG_ENV_SPI_CS		110
+#define CONFIG_SYS_SSP_PORT		2
+
 /*
  * mv-common.h should be defined after CMD configs since it used them
  * to enable certain macros
-- 
1.7.0.4