[U-Boot] [PATCH v2 1/4] SPI: Add SPI driver support for Marvell Armada100
Ajay Bhargav
ajay.bhargav at einfochips.com
Wed Sep 21 09:00:57 CEST 2011
This patch provides support for SPI emulated over SSP for Marvell
Armada100 SOC.
Signed-off-by: Ajay Bhargav <ajay.bhargav at einfochips.com>
---
Changes for v2:
- Code cleanup
arch/arm/include/asm/arch-armada100/spi.h | 95 ++++++++++++
drivers/spi/Makefile | 1 +
drivers/spi/armada100_spi.c | 228 +++++++++++++++++++++++++++++
3 files changed, 324 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/spi.h
create mode 100644 drivers/spi/armada100_spi.c
diff --git a/arch/arm/include/asm/arch-armada100/spi.h b/arch/arm/include/asm/arch-armada100/spi.h
new file mode 100644
index 0000000..58f0d8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/spi.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav at einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_SPI_H_
+#define __ARMADA100_SPI_H_
+
+#include <asm/arch/armada100.h>
+
+#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
+#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
+
+/*
+ * SSP Serial Port Registers
+ * refer Appendix A.26
+ */
+struct ssp_reg {
+ u32 sscr0; /* SSP Control Register 0 - 0x000 */
+ u32 sscr1; /* SSP Control Register 1 - 0x004 */
+ u32 sssr; /* SSP Status Register - 0x008 */
+ u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
+ u32 ssdr; /* SSP Data Register - 0x010 */
+ u32 pad1[5];
+ u32 ssto; /* SSP Timeout Register - 0x028 */
+ u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
+ u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
+ u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
+ u32 sstss; /* SSP Timeslot Status Register - 0x038 */
+};
+
+#define DEFAULT_WORD_LEN 8
+#define SSP_FLUSH_NUM 0x2000
+#define RX_THRESH_DEF 8
+#define TX_THRESH_DEF 8
+#define TIMEOUT_DEF 1000
+
+#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
+#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
+ setting */
+#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
+#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
+#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
+
+#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
+#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
+#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
+ Interrupt enable */
+
+#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
+#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
+#define SSCR0_FRF 0x30 /* FRame Format (mask) */
+#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
+ Peripheral Interface */
+#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
+ Serial Protocol (SSP) */
+#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
+#define SSCR0_ECS (1 << 6) /* External clock select */
+#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
+ Enable */
+
+#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
+#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
+#define SSSR_BSY (1 << 4) /* SSP Busy */
+#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
+#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
+#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
+#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
+
+#endif /* __ARMADA100_SPI_H_ */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 96c9642..84ad6fa 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libspi.o
COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o
COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o
+COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c
new file mode 100644
index 0000000..7384c9c
--- /dev/null
+++ b/drivers/spi/armada100_spi.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav at einfochips.com>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Based on SSP driver
+ * Written-by: Lei Wen <leiwen at marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/io.h>
+#include <asm/arch/spi.h>
+#include <asm/gpio.h>
+
+#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
+
+struct armd_spi_slave {
+ struct spi_slave slave;
+ struct ssp_reg *spi_reg;
+ u32 cr0, cr1;
+ u32 int_cr1;
+ u32 clear_sr;
+ const void *tx;
+ void *rx;
+ int gpio_cs_inverted;
+};
+
+static int spi_armd_write(struct armd_spi_slave *pss)
+{
+ int wait_timeout = SSP_FLUSH_NUM;
+ while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_TNF))
+ ;
+ if (!wait_timeout) {
+ debug("%s: timeout error\n", __func__);
+ return -1;
+ }
+
+ if (pss->tx != NULL) {
+ writel(*(u8 *)pss->tx, &pss->spi_reg->ssdr);
+ ++pss->tx;
+ } else {
+ writel(0, &pss->spi_reg->ssdr);
+ }
+ return 0;
+}
+
+static int spi_armd_read(struct armd_spi_slave *pss)
+{
+ int wait_timeout = SSP_FLUSH_NUM;
+ while (--wait_timeout && !(readl(&pss->spi_reg->sssr) & SSSR_RNE))
+ ;
+ if (!wait_timeout) {
+ debug("%s: timeout error\n", __func__);
+ return -1;
+ }
+
+ if (pss->rx != NULL) {
+ *(u8 *)pss->rx = readl(&pss->spi_reg->ssdr);
+ ++pss->rx;
+ } else {
+ readl(&pss->spi_reg->ssdr);
+ }
+ return 0;
+}
+
+static int spi_armd_flush(struct armd_spi_slave *pss)
+{
+ unsigned long limit = SSP_FLUSH_NUM;
+
+ do {
+ while (readl(&pss->spi_reg->sssr) & SSSR_RNE)
+ readl(&pss->spi_reg->ssdr);
+ } while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--);
+
+ writel(SSSR_ROR, &pss->spi_reg->sssr);
+
+ return limit;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct armd_spi_slave *pss = to_armd_spi_slave(slave);
+
+ gpio_set_value(slave->cs, pss->gpio_cs_inverted);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct armd_spi_slave *pss = to_armd_spi_slave(slave);
+
+ gpio_set_value(slave->cs, !pss->gpio_cs_inverted);
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct armd_spi_slave *pss;
+
+ pss = malloc(sizeof(*pss));
+ if (!pss)
+ return NULL;
+
+ pss->slave.bus = bus;
+ pss->slave.cs = cs;
+ pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT);
+
+ pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE;
+
+ pss->cr1 = (SSCR1_RXTRESH(RX_THRESH_DEF) & SSCR1_RFT) |
+ (SSCR1_TXTRESH(TX_THRESH_DEF) & SSCR1_TFT);
+ pss->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
+ pss->cr1 |= (((mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
+ | (((mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
+
+ pss->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
+ pss->clear_sr = SSSR_ROR | SSSR_TINT;
+
+ pss->gpio_cs_inverted = mode & SPI_CS_HIGH;
+ gpio_set_value(cs, !pss->gpio_cs_inverted);
+
+ return &pss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct armd_spi_slave *pss = to_armd_spi_slave(slave);
+
+ free(pss);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct armd_spi_slave *pss = to_armd_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+ if (spi_armd_flush(pss) == 0)
+ return -1;
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct armd_spi_slave *pss = to_armd_spi_slave(slave);
+ uint bytes = bitlen / 8;
+ unsigned long limit;
+ int ret = 0;
+
+ if (bitlen == 0)
+ goto done;
+
+ /* we can only do 8 bit transfers */
+ if (bitlen % 8) {
+ flags |= SPI_XFER_END;
+ goto done;
+ }
+
+ if (dout)
+ pss->tx = dout;
+ else
+ pss->tx = NULL;
+
+ if (din)
+ pss->rx = din;
+ else
+ pss->rx = NULL;
+
+ if (flags & SPI_XFER_BEGIN) {
+ spi_cs_activate(slave);
+ writel(pss->cr1 | pss->int_cr1, &pss->spi_reg->sscr1);
+ writel(TIMEOUT_DEF, &pss->spi_reg->ssto);
+ writel(pss->cr0, &pss->spi_reg->sscr0);
+ }
+
+ while (bytes--) {
+ limit = SSP_FLUSH_NUM;
+ ret = spi_armd_write(pss);
+ if (ret)
+ break;
+
+ while ((readl(&pss->spi_reg->sssr) & SSSR_BSY) && limit--)
+ udelay(1);
+
+ ret = spi_armd_read(pss);
+ if (ret)
+ break;
+ }
+
+ done:
+ if (flags & SPI_XFER_END) {
+ /* Stop SSP */
+ writel(pss->clear_sr, &pss->spi_reg->sssr);
+ clrbits_le32(&pss->spi_reg->sscr1, pss->int_cr1);
+ writel(0, &pss->spi_reg->ssto);
+ spi_cs_deactivate(slave);
+ }
+
+ return ret;
+}
--
1.7.0.4
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