[U-Boot] [PATCH 1/4] MX5: Modify the PLL decoding algorithm

[Stefano Babic]

On 09/22/2011 05:20 AM, Jason Hui wrote:
> On Thu, Sep 15, 2011 at 8:09 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> The PLL decoding algorithm didn't take into account many configuration bits.
>> Adjust it according to Linux kernel. Also, add PLL4 for MX53.
>>
>> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>> ---
>>  arch/arm/cpu/armv7/mx5/clock.c           |   77 ++++++++++++++++++++++++++----
>>  arch/arm/include/asm/arch-mx5/imx-regs.h |    3 +
>>  2 files changed, 70 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
>> index 00610a0..9f37f7f 100644
>> --- a/arch/arm/cpu/armv7/mx5/clock.c
>> +++ b/arch/arm/cpu/armv7/mx5/clock.c
>> @@ -29,11 +29,13 @@
>>  #include <asm/arch/imx-regs.h>
>>  #include <asm/arch/crm_regs.h>
>>  #include <asm/arch/clock.h>
>> +#include <div64.h>
>>
>>  enum pll_clocks {
>>        PLL1_CLOCK = 0,
>>        PLL2_CLOCK,
>>        PLL3_CLOCK,
>> +       PLL4_CLOCK,
>>        PLL_CLOCKS,
>>  };
>>
>> @@ -41,25 +43,76 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
>>        [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
>>        [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
>>        [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
>> +#ifdef CONFIG_MX53
>> +       [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
>> +#endif
>>  };
>>
>> +#define        MXC_DPLLC_CTL_HFSM              (1 << 7)
>> +#define        MXC_DPLLC_CTL_DPDCK0_2_EN       (1 << 12)
>> +
>> +#define        MXC_DPLLC_OP_PDF_MASK           0xf
>> +#define        MXC_DPLLC_OP_MFI_MASK           (0xf << 4)
>> +#define        MXC_DPLLC_OP_MFI_OFFSET         4
>> +
>> +#define        MXC_DPLLC_MFD_MFD_MASK          0x7ffffff
>> +
>> +#define        MXC_DPLLC_MFN_MFN_MASK          0x7ffffff
> 
> Can we put this stuff to crm_reg.h file?

Right. Clock related defines are in the crm_reg.h file

Best regards,
Stefano Babic

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