[U-Boot] [PATCH 2/2] mpc85xx: support for Freescale COM Express P2020

Ira W. Snyder iws at ovro.caltech.edu
Tue Sep 27 23:30:46 CEST 2011


This adds support for the Freescale COM Express P2020 board. This board
is similar to the P1_P2_RDB, but has some extra (as well as missing)
peripherals.

Unlike all other mpc85xx boards, it uses a watchdog timeout to reset.
Using the HRESET_REQ register does not work.

Signed-off-by: Ira W. Snyder <iws at ovro.caltech.edu>
---
 arch/powerpc/include/asm/immap_85xx.h |    1 +
 board/freescale/p2020come/Makefile    |   53 +++
 board/freescale/p2020come/ddr.c       |  245 +++++++++++++
 board/freescale/p2020come/law.c       |   36 ++
 board/freescale/p2020come/p2020come.c |  393 ++++++++++++++++++++
 board/freescale/p2020come/pci.c       |   43 +++
 board/freescale/p2020come/tlb.c       |   91 +++++
 boards.cfg                            |    3 +
 include/configs/P2020COME.h           |  638 +++++++++++++++++++++++++++++++++
 9 files changed, 1503 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/p2020come/Makefile
 create mode 100644 board/freescale/p2020come/ddr.c
 create mode 100644 board/freescale/p2020come/law.c
 create mode 100644 board/freescale/p2020come/p2020come.c
 create mode 100644 board/freescale/p2020come/pci.c
 create mode 100644 board/freescale/p2020come/tlb.c
 create mode 100644 include/configs/P2020COME.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 6aaade0..7b9f5b0 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2370,6 +2370,7 @@ typedef struct ccsr_usb_phy {
 #define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		0x22000
+#define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
 #else
diff --git a/board/freescale/p2020come/Makefile b/board/freescale/p2020come/Makefile
new file mode 100644
index 0000000..8b05be7
--- /dev/null
+++ b/board/freescale/p2020come/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB			= $(obj)lib$(BOARD).o
+
+COBJS-y			+= $(BOARD).o
+COBJS-y			+= ddr.o
+COBJS-y			+= law.o
+COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-y			+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
new file mode 100644
index 0000000..dd2a4dd
--- /dev/null
+++ b/board/freescale/p2020come/ddr.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright 2009, 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0x43000000	/* Type = DDR2*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000000
+#define CONFIG_SYS_DDR_TIMING_5		0x00000000
+
+#define CONFIG_SYS_DDR_TIMING_3_400	0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_400	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_400	0x39355322
+#define CONFIG_SYS_DDR_TIMING_2_400	0x1f9048ca
+#define CONFIG_SYS_DDR_CLK_CTRL_400	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_400	0x00480432
+#define CONFIG_SYS_DDR_MODE_2_400	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_400	0x06180100
+
+#define CONFIG_SYS_DDR_TIMING_3_533	0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_533	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1_533	0x4c47c432
+#define CONFIG_SYS_DDR_TIMING_2_533	0x0f9848ce
+#define CONFIG_SYS_DDR_CLK_CTRL_533	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_533	0x00040642
+#define CONFIG_SYS_DDR_MODE_2_533	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_533	0x08200100
+
+#define CONFIG_SYS_DDR_TIMING_3_667	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_667	0x55770802
+#define CONFIG_SYS_DDR_TIMING_1_667	0x5f599543
+#define CONFIG_SYS_DDR_TIMING_2_667	0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_667	0x03000000
+#define CONFIG_SYS_DDR_MODE_1_667	0x00040852
+#define CONFIG_SYS_DDR_MODE_2_667	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667	0x0a280100
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00040000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x00770802
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b6543
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0fa074d1
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00040852
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0c300100
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
+	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
+	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+	char buf[32];
+	fsl_ddr_cfg_regs_t ddr_cfg_regs;
+	size_t ddr_size;
+	struct cpu_type *cpu;
+	ulong ddr_freq, ddr_freq_mhz;
+
+	cpu = gd->cpu;
+	/* P1020 and it's derivatives support max 32bit DDR width */
+	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
+		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
+	} else {
+		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+	}
+#if defined(CONFIG_SYS_RAMBOOT)
+	return ddr_size;
+#endif
+	ddr_freq = get_ddr_freq(0);
+	ddr_freq_mhz = ddr_freq / 1000000;
+
+	printf("Configuring DDR for %s MT/s data rate\n",
+				strmhz(buf, ddr_freq));
+
+	if (ddr_freq_mhz <= 400)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
+	else if (ddr_freq_mhz <= 533)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
+	else if (ddr_freq_mhz <= 667)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
+	else if (ddr_freq_mhz <= 800)
+		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
+	else
+		panic("Unsupported DDR data rate %s MT/s data rate\n",
+					strmhz(buf, ddr_freq));
+
+	/* P1020 and it's derivatives support max 32bit DDR width */
+	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
+		cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
+		ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+		ddr_cfg_regs.cs[0].bnds = 0x0000001F;
+	}
+
+	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+	set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
+	return ddr_size;
+}
diff --git a/board/freescale/p2020come/law.c b/board/freescale/p2020come/law.c
new file mode 100644
index 0000000..56508db
--- /dev/null
+++ b/board/freescale/p2020come/law.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020come/p2020come.c b/board/freescale/p2020come/p2020come.c
new file mode 100644
index 0000000..e558c58
--- /dev/null
+++ b/board/freescale/p2020come/p2020come.c
@@ -0,0 +1,393 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <mmc.h>
+#include <malloc.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * GPIO
+ * 0 - 3: CarryBoard Input;
+ * 4 - 7: CarryBoard Output;
+ * 8 : Mux as SDHC_CD (card detection)
+ * 9 : Mux as SDHC_WP
+ * 10 : Clear Watchdog timer
+ * 11 : LED Input
+ * 12 : Output to 1
+ * 13 : Open Drain
+ * 14 : LED Output
+ * 15 : Switch Input
+ */
+#define GPIO_DIR		0x0f3a0000
+#define GPIO_ODR		0x00000000
+
+#define BOARD_PERI_RST_SET	(VSC7385_RST_SET | SLIC_RST_SET | \
+				 SGMII_PHY_RST_SET | PCIE_RST_SET | \
+				 RGMII_PHY_RST_SET)
+
+#define SYSCLK_MASK	0x00200000
+#define BOARDREV_MASK	0x10100000
+#define BOARDREV_B	0x10100000
+#define BOARDREV_C	0x00100000
+#define BOARDREV_D	0x00000000
+
+#define SYSCLK_66	66666666
+#define SYSCLK_50	50000000
+#define SYSCLK_100	100000000
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+	switch (ddr_ratio) {
+	case 0x0C:
+		return SYSCLK_66;
+	case 0x0A:
+	case 0x08:
+		return SYSCLK_100;
+	default:
+		puts("ERROR: unknown DDR ratio\n");
+		return SYSCLK_100;
+	}
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
+
+	ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+	switch (ddr_ratio) {
+	case 0x0C:
+	case 0x0A:
+		return SYSCLK_66;
+	case 0x08:
+		return SYSCLK_100;
+	default:
+		puts("ERROR: unknown DDR ratio\n");
+		return SYSCLK_100;
+	}
+}
+
+#ifdef CONFIG_MMC
+int board_early_init_f(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+			(MPC85xx_PMUXCR_SDHC_CD |
+			 MPC85xx_PMUXCR_SDHC_WP));
+
+	/* All the device are enable except for SRIO12 */
+	setbits_be32(&gur->devdisr, 0x80000);
+	return 0;
+}
+#endif
+
+int checkboard(void)
+{
+	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
+
+	/*
+	 * GPIO
+	 * 0 - 3: CarryBoard Input;
+	 * 4 - 7: CarryBoard Output;
+	 * 8 : Mux as SDHC_CD (card detection)
+	 * 9 : Mux as SDHC_WP
+	 * 10 : Clear Watchdog timer
+	 * 11 : LED Input
+	 * 12 : Output to 1
+	 * 13 : Open Drain
+	 * 14 : LED Output
+	 * 15 : Switch Input
+	 *
+	 * Set GPIOs 11, 12, 14 to 1.
+	 */
+	out_be32(&pgpio->gpdir, GPIO_DIR);
+	out_be32(&pgpio->gpodr, GPIO_ODR);
+	out_be32(&pgpio->gpdat, 0x001A0000);
+
+	puts("Board: Freescale COM Express P2020\n");
+	return 0;
+}
+
+#define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
+
+static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
+{
+	u8 data;
+
+	if (i2c_read(0x68, reg, 1, &data, 1)) {
+		M41ST85W_ERROR("unable to read %s bit\n", name);
+		return;
+	}
+
+	if (data & mask) {
+		data &= ~mask;
+		if (i2c_write(0x68, reg, 1, &data, 1)) {
+			M41ST85W_ERROR("unable to clear %s bit\n", name);
+			return;
+		}
+	}
+}
+
+/*
+ * The P2020COME board has a STMicro M41ST85W RTC/watchdog
+ * at i2c bus 1 address 0x68.
+ */
+static void start_rtc(void)
+{
+	unsigned int bus = i2c_get_bus_num();
+
+	if (i2c_set_bus_num(1)) {
+		M41ST85W_ERROR("unable to set i2c bus\n");
+		goto out;
+	}
+
+	/* ensure ST (stop) and HT (halt update) bits are cleared */
+	m41st85w_clear_bit(0x1, 0x80, "ST");
+	m41st85w_clear_bit(0xc, 0x40, "HT");
+
+out:
+	/* reset the i2c bus */
+	i2c_set_bus_num(bus);
+}
+
+int board_early_init_r(void)
+{
+	start_rtc();
+	return 0;
+}
+
+void board_reset(void)
+{
+	u8 data = (1 << 2) | 0x82;
+
+	/* set the hardware watchdog timeout to 1 second, then hang */
+	i2c_set_bus_num(1);
+	i2c_write(0x68, 9, 1, &data, 1);
+
+	while (1)
+		/* hang */;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (is_serdes_configured(SGMII_TSEC3)) {
+		puts("eTSEC3 is in sgmii mode.");
+		tsec_info[num].flags |= TSEC_SGMII;
+	}
+	num++;
+#endif
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void fdt_fixup_add_2nd_usb(void *blob, int agent)
+{
+	const char *soc_compat = "fsl,p2020-immr";
+	const char *lbc_compat = "fsl,p2020-elbc";
+	const u32 *addrcell, *sizecell, *ph;
+	int off, lbcoff, len, err;
+	u32 *regbuf = NULL;
+	u32 *irqbuf = NULL;
+
+	off = fdt_node_offset_by_compatible(blob, -1, soc_compat);
+	if (off < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+			soc_compat, fdt_strerror(off));
+		return;
+	}
+
+	lbcoff = fdt_node_offset_by_compatible(blob, -1, lbc_compat);
+	if (lbcoff < 0) {
+		printf("WARNING: could not find compatible node %s: %s.\n",
+			lbc_compat, fdt_strerror(lbcoff));
+		return;
+	}
+
+	addrcell = fdt_getprop(blob, off, "#address-cells", NULL);
+	sizecell = fdt_getprop(blob, off, "#size-cells", NULL);
+
+	off = fdt_add_subnode(blob, off, "usb at 23000");
+	if (off < 0) {
+		printf("WARNING: could not add 2nd usb node %s.\n",
+				fdt_strerror(off));
+		return;
+	}
+
+	err = fdt_setprop_cell(blob, off, "#address-cells", 1);
+	if (err < 0)
+		printf("WARNING: could not set #address-cell property: %s\n",
+			fdt_strerror(err));
+
+	err = fdt_setprop_cell(blob, off, "#size-cells", 0);
+	if (err < 0)
+		printf("WARNING: could not set #size-cells property: %s\n",
+			fdt_strerror(err));
+
+	err = fdt_setprop_string(blob, off, "compatible", "fsl-usb2-dr");
+	if (err < 0)
+		printf("WARNING: could not set compatible property: %s\n",
+			fdt_strerror(err));
+
+	err = fdt_setprop_string(blob, off, "phy_type", "ulpi");
+	if (err < 0)
+		printf("WARNING: could not set phy_type property: %s\n",
+			fdt_strerror(err));
+
+	if (agent) {
+		err = fdt_setprop_string(blob, off, "dr_mode", "peripheral");
+		if (err < 0)
+			printf("WARNING: could not set dr_mode property: %s\n",
+				fdt_strerror(err));
+	}
+
+	if (addrcell && *addrcell == 2) {
+		regbuf[0] = 0;
+		regbuf[1] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
+		len = 2;
+	} else {
+		regbuf[0] = CONFIG_SYS_MPC85xx_USB2_OFFSET;
+		len = 1;
+	}
+
+	if (sizecell && *sizecell == 2) {
+		regbuf[len] = 0;
+		regbuf[len + 1] = 0x1000;
+		len = 2;
+	} else {
+		regbuf[len] = 0x1000;
+		len++;
+	}
+
+	err = fdt_setprop(blob, off, "reg", regbuf, len * sizeof(u32));
+	if (err < 0)
+		printf("WARNING: could not set <%s> %s\n",
+					"reg", fdt_strerror(err));
+
+	irqbuf[0] = 0x2e;
+	irqbuf[1] = 0x2;
+
+	err = fdt_setprop(blob, off, "interrupts", irqbuf, 2 * sizeof(u32));
+	if (err < 0)
+		printf("WARNING: could not set %s %s\n",
+				"interrupts", fdt_strerror(err));
+
+	ph = fdt_getprop(blob, lbcoff, "interrupt-parent", 0);
+	if (!ph) {
+		printf("WARNING: could not read interrupt-parent property\n");
+		return;
+	}
+
+	err = fdt_setprop(blob, off, "interrupt-parent", ph, sizeof(u32));
+	if (err < 0)
+		printf("WARNING: could not set %s %s\n",
+				"interrupt-parent", fdt_strerror(err));
+}
+
+extern void ft_pci_board_setup(void *blob);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+	int agent;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	ft_pci_board_setup(blob);
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+	if (!hwconfig("usb2"))
+		return;
+
+	agent = hwconfig_subarg_cmp("usb2", "dr_mode", "peripheral");
+
+	/*
+	 * Add the 2nd usb node and enable it. eLBC will
+	 * now be disabled since it is MUXed with USB2
+	 */
+
+	fdt_fixup_add_2nd_usb(blob, agent);
+}
+#endif
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p2020come/pci.c b/board/freescale/p2020come/pci.c
new file mode 100644
index 0000000..bd1a91e
--- /dev/null
+++ b/board/freescale/p2020come/pci.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+#include <asm/io.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void ft_pci_board_setup(void *blob)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/p2020come/tlb.c b/board/freescale/p2020come/tlb.c
new file mode 100644
index 0000000..7be8584
--- /dev/null
+++ b/board/freescale/p2020come/tlb.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+			MAS3_SX|MAS3_SW|MAS3_SR, 0,
+			0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 1, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_PCI)
+	/* *I*G* - PCI3 - PCI2 0x8000,0000 - 0xbfff,ffff, size = 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 2, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI1 0xC000,0000 - 0xcfff,ffff, size = 256M */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_VIRT,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 3, BOOKE_PAGESZ_256M, 1),
+
+
+	/* *I*G* - PCI1  0xD000,0000 - 0xDFFF,FFFF, size = 256M */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O  PCI3 => 0xFFC10000 ;  PCI2 => 0xFFC2,0000 ; PCI1 => 0xFFC3,0000 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 5, BOOKE_PAGESZ_256K, 1),
+#endif /* #if defined(CONFIG_PCI) */
+
+#if defined(CONFIG_SYS_RAMBOOT)
+	/* *I*G - DDR3  2G     Part 1: 0 - 0x3fff,ffff , size = 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 6, BOOKE_PAGESZ_1G, 1),
+	/*        DDR3  2G     Part 2: 0x4000,0000 - 0x7fff,ffff , size = 1G */
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_1G, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 8a5bfc1..e1be366 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -606,6 +606,9 @@ P2020RDB_36BIT_SPIFLASH      powerpc     mpc85xx     p1_p2_rdb           freesca
 P2020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,NAND
 P2020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SDCARD
 P2020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2020RDB,SPIFLASH
+P2020COME_NAND               powerpc     mpc85xx     p2020come           freescale      -           P2020COME:NAND
+P2020COME_SDCARD             powerpc     mpc85xx     p2020come           freescale      -           P2020COME:SDCARD
+P2020COME_SPIFLASH           powerpc     mpc85xx     p2020come           freescale      -           P2020COME:SPIFLASH
 P2041RDB                     powerpc     mpc85xx     p2041rdb            freescale
 P2041RDB_SDCARD              powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 P2041RDB_SPIFLASH            powerpc     mpc85xx     p2041rdb            freescale      -           P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h
new file mode 100644
index 0000000..60c0809
--- /dev/null
+++ b/include/configs/P2020COME.h
@@ -0,0 +1,638 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_P2020		1
+#define CONFIG_P2020COME	1
+
+/*
+ * Boot using DDR for eSDHC/eSPI/NAND boot because L2 Cache size
+ * on these platforms is 256K.
+ */
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL	0xfff00000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_LDSCRIPT		$(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_TEXT_BASE		0xf8f82000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
+#define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (slot 3) */
+
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		1	/* E1000 pci Ethernet card */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+/*
+ * For P2020COME DDRCLK and SYSCLK are from the same oscillator
+ * For DA phase the SYSCLK is 66MHz
+ * For EA phase the SYSCLK is 100MHz
+ */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0)
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
+#define CONFIG_MP
+#endif
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch prediction */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+
+
+
+
+
+
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ULL
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR
+#endif
+							/* CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
+							/* CONFIG_SYS_IMMR */
+
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#endif
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+#define CONFIG_SYS_SDRAM_SIZE		2048ULL	/* DDR size on P2020COME */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00FF0000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR3			2G Cacheable
+ * 0x8000_0000	0x9fff_ffff	PCI Express 3 Mem	1G non-cacheable
+ * 0xa000_0000	0xbfff_ffff	PCI Express 2 Mem	1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI Express 1 Mem	1G non-cacheable
+ * 0xffc1_0000	0xffc1_ffff	PCI Express 3 IO	64K non-cacheable
+ * 0xffc2_0000	0xffc2_ffff	PCI Express 2 IO	64K non-cacheable
+ * 0xffc3_0000	0xffc3_ffff	PCI Express 1 IO	64K non-cacheable
+ *
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* There is no NOR Flash on P2020COME */
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+    defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	CONFIG_SYS_INIT_RAM_ADDR
+/* the assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE   \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* new uImage format support */
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef  CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}  /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR2	0x18
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#if defined(CONFIG_PCI)
+
+/* controller 3, Slot 3, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000  /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000  /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000  /* 64k */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE		0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif	/* CONFIG_PCI */
+
+#define CONFIG_NET_MULTI	1
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		2
+#define TSEC3_PHY_ADDR		1
+
+#undef CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+	#define CONFIG_ENV_IS_IN_MMC	1
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+	#define CONFIG_ENV_IS_IN_SPI_FLASH
+	#define CONFIG_ENV_SPI_BUS	0
+	#define CONFIG_ENV_SPI_CS	0
+	#define CONFIG_ENV_SPI_MAX_HZ	10000000
+	#define CONFIG_ENV_SPI_MODE	0
+	#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+	#define CONFIG_ENV_SECT_SIZE	0x10000
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+	#define CONFIG_ENV_ADDR		0xfff80000
+	#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#endif
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC	1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif /* CONFIG_MMC */
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Misc Extra Settings */
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+#define CONFIG_CMD_DHCP			1
+
+#define CONFIG_CMD_DATE			1
+#define CONFIG_RTC_M41T62		1
+#define CONFIG_SYS_RTC_BUS_NUM		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support   */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootcmd=run sdboot\0"						\
+	"sdboot=setenv bootargs root=/dev/mmcblk0p2 rw "		\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "	\
+		"$othbootargs; mmcinfo; "				\
+		"ext2load mmc 0:2 $loadaddr /boot/$bootfile; "		\
+		"ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; "		\
+		"bootm $loadaddr - $fdtaddr\0"				\
+	"sdfatboot=setenv bootargs root=/dev/ram rw "			\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "	\
+		"$othbootargs; mmcinfo; "				\
+		"fatload mmc 0:1 $loadaddr $bootfile; "			\
+		"fatload mmc 0:1 $fdtaddr $fdtfile; "			\
+		"fatload mmc 0:1 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbboot=setenv bootargs root=/dev/sda1 rw "			\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "	\
+		"$othbootargs; "					\
+		"usb start; "						\
+		"ext2load usb 0:1 $loadaddr /boot/$bootfile; "		\
+		"ext2load usb 0:1 $fdtaddr /boot/$fdtfile; "		\
+		"bootm $loadaddr - $fdtaddr\0"				\
+	"usbfatboot=setenv bootargs root=/dev/ram rw "			\
+		"console=$consoledev,$baudrate $othbootargs; "		\
+		"usb start; "						\
+		"fatload usb 0:2 $loadaddr $bootfile; "			\
+		"fatload usb 0:2 $fdtaddr $fdtfile; "			\
+		"fatload usb 0:2 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "			\
+		"console=$consoledev,$baudrate $othbootargs; "		\
+		"usb start; "						\
+		"ext2load usb 0:4 $loadaddr $bootfile; "		\
+		"ext2load usb 0:4 $fdtaddr $fdtfile; "			\
+		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"upgradespi=sf probe 0; "					\
+		"setenv startaddr 0; "					\
+		"setenv erasesize a0000; "				\
+		"tftp 1000000 $tftppath/$uboot_spi; "			\
+		"sf erase $startaddr $erasesize; "			\
+		"sf write 1000000 $startaddr $filesize; "		\
+		"sf erase 100000 120000\0"				\
+	"clearspienv=sf probe 0;sf erase 100000 20000\0"		\
+	"othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0"	\
+	"netdev=eth0\0"							\
+	"rootdelaysecond=15\0"						\
+	"uboot_nor=u-boot-nor.bin\0"					\
+	"uboot_spi=u-boot-p2020.spi\0"					\
+	"uboot_sd=u-boot-p2020.bin\0"					\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=rootfs-dev.ext2.img\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=uImage-2.6.32-p2020.dtb\0"				\
+	"tftppath=p2020\0"
+
+#define CONFIG_HDBOOT							\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"usb start;"							\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"			\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $loadaddr $tftppath/$bootfile;"				\
+	"tftp $fdtaddr $tftppath/$fdtfile;"				\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $ramdiskaddr $tftppath/$ramdiskfile;"			\
+	"tftp $loadaddr $tftppath/$bootfile;"				\
+	"tftp $fdtaddr $tftppath/$fdtfile;"				\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif  /* __CONFIG_H */
-- 
1.7.3.4



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